Topological Crack Stop Passivation for Via Crack Reliability
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Solution Overview
Problem
Integrated circuits in advanced driver-assistance systems (ADAS) face reliability issues due to die passivation cracks that propagate and cause electrical discontinuities, leading to premature failure during thermal cycling stress tests, with existing solutions like using polyimide passivation material being costly and impractical, smaller dies reducing feature count, and removing lids compromising thermal performance.
Innovation Solution
Implementing a topological crack stop (TCS) passivation layer with tailored features to arrest crack propagation, using materials such as inorganic dielectrics, metals, or their combinations, integrated into both front-end-of-line (FEOL) and back-end-of-line (BEOL) semiconductor processing to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional passivation methods are used, then manufacturing cost is reduced, but die passivation cracks occur leading to electrical discontinuity
Solution Approach 1:
The passivation layer is segmented by introducing topological crack stop (TCS) features that divide the continuous layer into sections. These TCS features act as crack arrestors, preventing crack propagation across the entire passivation layer while maintaining the structural integrity and electrical continuity of the IC structure.
Solution Approach 2:
The TCS features serve as intermediary elements between the passivation layer and the underlying structure. These features are specifically designed to intercept and stop crack propagation, acting as a mediator that prevents cracks from reaching critical components while maintaining the overall functionality of the passivation system.
2Reliability
If polyimide passivation is used, then crack propagation is arrested, but feature density and heat conduction are reduced
Solution Approach 1:
Instead of using polyimide material throughout the entire passivation layer, the invention applies TCS features locally at strategic positions where crack propagation is most likely to occur. This localized approach provides crack arrestor functionality only where needed, preserving the high feature density and heat conduction properties of the underlying passivation layer in other regions.
Solution Approach 2:
The invention creates a composite structure by integrating TCS features into the passivation layer. This composite approach combines the crack-resistant properties of TCS features with the high-density and high thermal conductivity properties of conventional passivation materials, achieving both reliability and productivity goals simultaneously.
3Reliability
If polyimide passivation is used, then crack propagation is arrested, but heat conduction is reduced
Solution Approach 1:
The TCS features are strategically positioned to provide crack arrestor functionality only at critical locations, allowing the bulk of the passivation layer to maintain its superior heat conduction properties. This localized application ensures that thermal management is not compromised while achieving the desired crack resistance.
Solution Approach 2:
The composite structure of TCS features integrated into the passivation layer combines the thermal conductivity benefits of conventional materials with the crack-resistant properties of TCS features, achieving both reliability and thermal performance without the energy loss associated with full polyimide replacement.
4Productivity
If scaling is extended to sub-10 nm range, then device capacity is increased, but fabrication variability limits further extension
Solution Approach 1:
The TCS features are incorporated into the passivation layer during the fabrication process at an early stage, before final device assembly. This preliminary action ensures that crack prevention mechanisms are already in place, compensating for fabrication variability and enabling reliable scaling to sub-10 nm nodes without requiring perfect fabrication precision throughout the entire process.
Data Source
Figure 1~2A
Figure 2B~2C
Figure 3A~3C
AI summary
An integrated circuit structure comprises one or more first level interconnects (FLIs) embedded in an underfill (UF) over a substrate. An etch stop layer is over the FLIs. A passivation layer is over the etch stop layer and a plurality of vias are through the passivation layer. A plurality of contacts are on the passivation layer in contact with the vias to connect with the FLI. A plurality of topological crack stop (TCS) features are formed in the passivation layer and on a top surface of the etch stop layer.