Block Erase Write Operation for CBRAM Memory Power Reduction
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Solution Overview
Problem
Conventional memory devices face challenges in reducing power consumption, particularly during erase operations, due to the significant power required for charging and discharging the common conductor in conductive bridge random access memory (CBRAM) cells.
Innovation Solution
Implementing a block erase write operation that simultaneously erases all memory cells of a sub-tile or multiple sub-tiles, reducing the number of charge/discharge cycles and thereby lowering power consumption and increasing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If individual page erase operations are performed in conventional memory devices, then complete erase functionality is achieved, but power consumption increases and throughput decreases
Solution Approach 1:
The patent merges multiple individual page erase operations into a single block erase operation. By combining the erase functionality across multiple pages into one unified operation, the system performs all necessary charge/discharge cycles simultaneously, reducing total power consumption while increasing erase throughput compared to sequential page erasures.
2Reliability
If multiple charge/discharge cycles are performed for each page erase, then thorough erasure is achieved, but power consumption increases
Solution Approach 1:
The patent combines the charge/discharge cycles required for multiple pages into a single coordinated operation. By merging these cycles across all pages to be erased, the system achieves thorough erasure of all pages while performing the charge/discharge operations simultaneously rather than sequentially, thereby reducing total power consumption.
3Ease of operation
If sequential page erase operations are used, then individual page control is maintained, but erase throughput decreases
Solution Approach 1:
The patent merges individual page erase operations into a block-level operation that maintains the ability to selectively erase specific pages within the block. By combining the erase functionality at the block level while preserving page-level selectivity through control signals, the system achieves both ease of operation and increased erase throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption by approximately half and doubles erase throughput compared to traditional methods that erase pages individually, achieving improved power efficiency and performance.
Implementation Method 1
A memory cell includes a memory element and an access transistor. The memory element has a first electrical resistance state corresponding to a first memory state of the memory cell and a second electrical resistance state corresponding to a second memory state of the memory cell
Implementation Method 2
A memory device includes a plurality of conductive bridge memory cells arranged in an array... Z common conductors each associated with one of the Z sub-tiles and the N conductive bridge memory cells of the one of the Z sub-tiles
Data Source
AI summary
Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.