CRAM Read Scheduling to Raise Error Detection Without Power Noise
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Solution Overview
Problem
Programmable logic devices face challenges in error detection due to single event upsets and tampering, where reading configuration random access memory (CRAM) cells can introduce noise and jitter on the power distribution network, potentially corrupting values and disrupting device operation.
Innovation Solution
Distributing CRAM reads temporally and spatially across the programmable logic device to avoid excessive instantaneous current draw, allowing for higher read rates while minimizing noise and jitter on the power distribution network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CRAM reads are performed frequently to increase error detection rate, then error detection capability is improved, but noise and jitter on the power distribution network increase
Solution Approach 1:
The patent divides the CRAM read operations into multiple segments distributed across different sectors. Each sector performs reads at different times rather than all simultaneously, segmenting the total current draw over time. This allows frequent overall error detection while preventing excessive instantaneous noise on the power distribution network.
Solution Approach 2:
The patent implements periodic CRAM read operations with controlled timing intervals. By scheduling reads periodically across different sectors with offset timing, the system maintains high error detection rates while ensuring that periodic current draws do not overlap in a way that would cause excessive noise or jitter on the power distribution network.
2Productivity
If multiple sectors perform CRAM reads simultaneously to increase error detection rate, then error detection speed is improved, but instantaneous current draw increases
Solution Approach 1:
The patent segments the CRAM read operations across multiple sectors with staggered timing. Instead of all sectors reading simultaneously, each sector is assigned a different time offset, which segments the instantaneous current draw while maintaining overall high productivity through parallel operation of multiple sectors.
Solution Approach 2:
The patent dynamically adjusts the timing of CRAM reads across different sectors based on power distribution network conditions. By making the read timing flexible and adaptive rather than fixed and simultaneous, the system can maintain high error detection rates while dynamically managing instantaneous current draw to prevent excessive power demands.
3Stability of the object's composition
If CRAM reads are distributed temporally and spatially to reduce instantaneous current draw, then power distribution stability is improved, but error detection rate may decrease
Solution Approach 1:
The patent segments CRAM reads across both space (different sectors) and time (different offsets), creating a distributed read pattern. This segmentation maintains power distribution stability by preventing current draw concentration, while the coordinated segmentation across multiple sectors ensures that the overall error detection rate remains high through parallel operation.
Solution Approach 2:
The patent ensures continuous error detection capability by overlapping CRAM read operations across different sectors. While individual sector reads are distributed in time to maintain power stability, the collective reads across all sectors provide continuous monitoring, preventing any gap in error detection capability and maintaining high productivity.
Data Source
AI summary
Methods and devices for increasing error detection rate while avoiding excessive power distribution network noise are provided. In one method, memory reads of configuration memory of a first group of sectors of a programmable logic device are performed. The memory reads start at a first start time within a first memory read period. The first memory read period includes an amount of time involved to perform one of the memory reads. The method also includes performing memory reads of configuration memory of a second group of sectors of the programmable logic device. The memory reads of the configuration memory of the second group of sectors start at a second start time within the first memory read period. The second start time is different from the first start time. By offsetting the start times of memory reads, power distribution noise may be reduced.