CBRAM Memory Device Erase Load Circuit Design
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Solution Overview
Problem
Conventional memory devices face limitations in erase current provision, particularly as access transistor sizes reduce, leading to insufficient erase current for strongly programmed elements and a limited range of erase voltages, which complicates the erase operation and introduces reliability issues.
Innovation Solution
The implementation of a memory device with a load circuit that allows for increased erase current by modulating the erase voltage, enabling the element to be reversibly programmed between multiple impedance states, including high resistance states with improved data retention, using a diode erase operation that surpasses conventional transistor erase capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If access transistor size is reduced, then device density is improved, but erase current capability deteriorates
Solution Approach 1:
The memory device is divided into separate program and erase operations with independent current paths. The erase operation uses a dedicated erase current path that does not share the access transistor with the program operation, allowing the transistor to be optimized for density while the erase path provides sufficient current for strongly programmed elements.
Solution Approach 2:
A load circuit is introduced as an intermediary component in the erase operation. This load circuit works in conjunction with the access transistor to provide the necessary erase current. The load circuit compensates for the reduced current capability of smaller transistors by providing additional current through its own operation.
2Area of moving object
If access transistor size is reduced, then device density is improved, but erase voltage range deteriorates
Solution Approach 1:
The erase operation dynamically adjusts the voltage applied to the memory element based on the strength of the programmed state. The system can adaptively select different erase voltages from a range, allowing sufficient voltage to be applied to strongly programmed elements while maintaining control over weakly programmed elements, despite the reduced capability of smaller transistors.
3Power
If erase current is increased, then erase effectiveness is improved, but operation complexity deteriorates
Solution Approach 1:
The erase operation is segmented into distinct operational phases with clear control signals. The separation of program and erase current paths allows each operation to be independently controlled and optimized, reducing the complexity of coordinating multiple current paths and voltage levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that erase current can equal or surpass program current, providing adequate reversal of programmed states and achieving tighter resistance distributions and greater modulation of erase resistance levels, thereby enhancing the control and efficiency of the erase operation.
Implementation Method 1
Within element 1501, metal atoms from the anode can oxidize and create a conductive path (i.e., filament) through a solid electrolyte layer
Implementation Method 2
Within element 1501, metal atoms making up any filament can oxidize, dissolving the filament
Implementation Method 3
A solid electrolyte formed between an anode 1505-0 and a cathode 1505-1
Data Source
AI summary
A memory device can include a plurality of two terminal conductive bridging random access memory (CBRAM) type memory elements; at least one program transistor configured to enable a program current to flow through at least one memory element in response to the application of a program signal at its control terminal and a program bias voltage to the memory element; and an erase load circuit that includes at least one two-terminal diode-like load element, the erase load circuit configured to enable an erase current to flow through the load element and at least one memory element in a direction opposite to that of the program current.