Multiple Crawbar Switching in Analog Signal Processing
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Solution Overview
Problem
Current CMOS active pixel sensor (APS) systems introduce noise when combining signals from different column buffer circuits in the digital domain, which can be mitigated by combining signals in the analog domain, but existing methods do not efficiently allow for concurrent reading and linear operations across multiple column buffer circuits.
Innovation Solution
A multiple crawbar switching method is implemented to programmatically access and combine signals from multiple column buffer circuits simultaneously in the analog domain, using a column decoder to select and process signals from multiple columns at once, and incorporating variable capacitors for operations like averaging and weighted sums.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If signals from multiple column buffer circuits are combined in the digital domain, then signal processing can be performed, but noise is introduced during the combination process
Solution Approach 1:
The patent introduces an analog summing circuit as an intermediary component between the column buffer circuits and the ADC. This summing circuit performs the combination of signals from multiple column buffers in the analog domain before digitization, thereby avoiding the noise that would be introduced by digital-domain combination. The intermediary analog circuit preserves signal quality while enabling multi-column processing.
Solution Approach 2:
The patent replaces the conventional digital-domain signal combination mechanism with an analog-domain mechanism. Instead of digitizing signals first and then combining them digitally (which introduces noise), the system substitutes this approach with analog summing circuits that combine signals in the voltage/charge domain before conversion, thereby eliminating the harmful digital combination noise.
2Productivity
If multiple column buffer circuits are accessed concurrently for signal combination, then processing efficiency is improved, but control complexity increases
Solution Approach 1:
The patent segments the control of multiple column buffer circuits into independent, modular components. Each column buffer can be selectively activated through individual control signals, and the analog summing circuit processes each column's contribution separately before combining them. This segmentation allows concurrent access to multiple columns while maintaining manageable control complexity through modular architecture.
Solution Approach 2:
The analog summing circuit is designed as a universal interface that can accept inputs from any combination of column buffer circuits simultaneously. The same summing infrastructure handles single-column and multi-column operations, as well as various linear operations (addition, subtraction, averaging), providing multi-functionality without requiring separate control mechanisms for each operation type.
3Object-generated harmful factors
If analog signal processing is performed across multiple column buffer circuits, then noise introduction is reduced, but existing methods lack efficiency for concurrent reading and linear operations
Solution Approach 1:
The patent enables continuous concurrent processing by allowing multiple column buffer circuits to be read out and processed simultaneously through the analog summing circuit. Unlike sequential methods that would process columns one at a time, this approach maintains continuous useful action by combining multiple column signals in parallel, thereby achieving both low noise introduction and high processing efficiency.
Solution Approach 2:
The system incorporates dynamic control capabilities that allow the analog summing circuit to adaptively process different combinations of column buffer circuits based on operational requirements. The control mechanism can dynamically select which columns to access and how to weight their contributions, enabling efficient concurrent processing with flexible linear operations while maintaining low noise levels.
Data Source
AI summary
An analog differential voltage circuit is disclosed that enables the combination of a plurality of voltage signals in the analog domain of a CMOS processing system prior to being received by a differential amplifier and prior to being digitized. By programming the column decoder to read out a plurality of column buffer circuits, a plurality of linear operations (e.g., addition, substation, averaging, weighted, sum) may be performed on the plurality of analog voltage levels prior to their being digitized.