Memory Channel CRC Bandwidth Overhead Reduction
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Solution Overview
Problem
Current memory systems face bandwidth penalties due to the use of cyclical redundancy check (CRC) protection, which affects the performance and efficiency of data transmission between the host and memory subsystems, particularly in high-speed memory operations.
Innovation Solution
The implementation of a method where data and CRC code are spread across multiple memory devices, including spare memory devices, allowing for CRC encoding without requiring additional bandwidth, by redistributing data across the DIMM during burst transactions and storing CRC codes within the memory devices, thus maintaining burst length and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CRC protection is implemented in memory systems, then data transmission reliability is improved, but bandwidth is reduced due to additional CRC code transmission
Solution Approach 1:
The patent divides the memory system into data memory devices and spare memory devices. CRC codes are generated for data bursts and stored in spare memory devices rather than transmitting additional CRC codes over the bus, segmenting the function of data storage and error detection across different memory resources.
Solution Approach 2:
The patent moves CRC code storage from the transmission dimension (bus bandwidth) to the storage dimension (spare memory devices). Instead of adding CRC transmission to the data bus, the system utilizes the vertical dimension of memory capacity in spare devices to store CRC codes, eliminating bandwidth overhead.
2Reliability
If CRC codes are transmitted with data, then error detection capability is improved, but latency increases due to additional transmission time
Solution Approach 1:
The patent generates and stores CRC codes in advance within the memory devices during normal write operations. When data is read, the CRC codes are already prepared and stored in spare memory devices, eliminating the need for real-time CRC calculation and transmission during read operations, thus reducing latency.
3Reliability
If additional bandwidth is allocated for CRC transmission, then CRC protection effectiveness is improved, but available bandwidth for data transmission is reduced
Solution Approach 1:
The patent makes spare memory devices serve dual functions: storing unused or redundant data and storing CRC codes for error detection. This multi-functionality allows the system to implement CRC protection without dedicating additional bandwidth resources, as the same spare memory capacity serves both purposes.
Data Source
AI summary
A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.