CRC Redundant Bit Interleaving for Early Error Detection
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Solution Overview
Problem
The existing CRC technique requires inputting all information bits for error detection, leading to delayed detection processes, and existing methods do not efficiently generate redundant bits for error detection using part of the information bits, resulting in decreased detection accuracy and increased computation.
Innovation Solution
A redundant bit generation device and method that dispersely arranges CRC-generated redundant bits within information bits using a permutation pattern based on the CRC polynomial, allowing for early error detection without inputting all information bits, utilizing on-off switches and cumulative adding mechanisms to generate and interleave redundant bits within the data string.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all information bits are input to the decoder for error detection using existing CRC technique, then detection accuracy is maintained, but detection time is delayed
Solution Approach 1:
The patent extracts only the necessary portion of information bits (a predetermined number of bits) required for error detection instead of processing all information bits. The CRC calculator generates redundant bits from these selected bits, enabling early error detection without waiting for the complete data block, thus reducing detection time while maintaining adequate detection accuracy.
Solution Approach 2:
The patent performs preliminary error detection by generating and checking redundant bits before the entire information block is received or processed. The CRC calculator computes redundant bits from a predetermined number of information bits as they become available, allowing early error detection and reducing the overall detection time while preserving detection capability.
2Reliability
If redundant bits are generated using existing polynomial division circuit with fixed coefficients, then error detection is performed, but detection accuracy decreases and computational overhead increases
Solution Approach 1:
The patent introduces dynamic switching of polynomial coefficients using switching elements. The coefficient switching controller changes the coefficients of the CRC polynomial based on the reception status of information bits, allowing the system to adapt the detection process. This dynamic coefficient adjustment enables accurate error detection while reducing computational overhead by modifying the polynomial based on available data.
Solution Approach 2:
The patent changes the parameters of the CRC polynomial (specifically the coefficients) during the error detection process. By switching between different coefficient sets based on reception status, the system optimizes the detection accuracy for different data states while reducing the computational burden compared to using fixed coefficients throughout the entire process.
Data Source
AI summary
A redundant bit generating device that generates redundant bits for error detection, that are added to a block of information bits, includes: a redundant bit calculation function that generates a predetermined number of redundant bits from the information bits according to a CRC polynomial; and a bit interleaving function that dispersedly arranges the predetermined number of redundant bits within the information bits using a permutation pattern determined based on the CRC polynomial.