CRC Code Generation Circuit for High-Density DRAM Error Detection

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Solution Overview

Problem

As DRAMs shrink in size, bit errors in memory cells increase, leading to decreased yield and operational efficiency, existing error detection methods in semiconductor memory devices are inadequate in effectively addressing these errors.

Innovation Solution

An error detection code generation circuit is introduced, comprising a first and second CRC engine and an output selection engine, using the same generation matrix to generate and merge error detection code bits based on unit data and DBI bits, enhancing error detection capabilities while reducing hardware overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If DRAM size is shrunk to increase storage capacity, then storage density is improved, but bit error rate increases

Engineering Contradiction:

Improvestorage densityVSAvoidbit error rate

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies preliminary action by generating error detection codes (CRC codes) before data is written to the DRAM. The encoding circuit processes the data and generates check bits in advance, which are stored together with the main data. When data is read back, the same encoding circuit can regenerate the expected CRC code and compare it with the stored CRC code to detect errors before they affect system operation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through the error detection and correction mechanism. The encoding circuit generates CRC codes that provide feedback information about data integrity. When errors are detected during read operations, the system can request retransmission or initiate error correction procedures, creating a closed-loop feedback system that maintains data reliability despite increased bit error rates from smaller cell sizes.

Inventive Principle:

Principle #23Feedback

2Device complexity

If traditional error detection methods are used, then implementation simplicity is maintained, but error detection capability is insufficient

Engineering Contradiction:

Improveimplementation simplicityVSAvoiderror detection capability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent applies parameter changes by utilizing cyclic redundancy check (CRC) codes, which are mathematical sequences with specific properties that enhance error detection capability. The encoding circuit implements CRC algorithms that generate check bits based on polynomial division, providing robust error detection for various error patterns including burst errors, single-bit errors, and double-bit errors, while maintaining reasonable hardware complexity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11223373B2Error detection code generation circuits of semiconductor devices, memory controllers including the same and semiconductor memory devices including the same

Publication Date: 2022.01.11 SAMSUNG ELECTRONICS CO LTD

AI summary

An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.