CRC Circuit Error Detection Pulse Separation
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Solution Overview
Problem
Current cyclic redundancy check (CRC) circuits in memory devices fail to accurately detect multiple CRC errors due to overlapping pulses when the time interval between errors is less than or equal to 12 clock cycles, leading to reduced reliability in data transmission processes.
Innovation Solution
A redesigned CRC circuit with a detection module generating a CRC signal for N errors and an alert signal generation module that uses delayed signals to produce distinct pulses for each error, ensuring the alert signal has at least one pulse width corresponding to the second preset time interval, thereby identifying multiple CRC errors effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional CRC circuit generates a single alert pulse for multiple CRC errors, then the circuit structure remains simple, but the reliability of error detection deteriorates when errors occur within 12 clock cycles of each other
Solution Approach 1:
The patent segments the error detection process into multiple stages by introducing a first delay unit and a second delay unit with different delay values. The first delay unit delays the CRC signal by a first delay value, and the second delay unit delays the first delayed signal by a second delay value. This segmentation allows the circuit to distinguish between multiple CRC errors that occur within 12 clock cycles of each other, thereby improving error detection reliability without excessive complexity increase.
Solution Approach 2:
The patent applies preliminary action by introducing a delay unit before the alert signal generation. The delay unit processes the CRC signal in advance, creating a time-shifted version of the signal. This preliminary processing enables the subsequent alert signal generation to accurately identify and separate multiple errors that occur close together in time, preventing them from being merged into a single alert pulse.
2Measurement precision
If the CRC circuit uses a simple alert signal generation without delay units, then the device complexity is low, but the measurement precision of error timing deteriorates
Solution Approach 1:
The patent introduces a delay unit that performs preliminary processing on the CRC signal before it reaches the alert signal generation stage. This delay unit creates a time-shifted version of the CRC signal, which enables precise measurement of error timing information. The delay value is specifically designed to be greater than 12 clock cycles, ensuring that errors occurring within 12 clock cycles of each other can be distinguished from each other.
Solution Approach 2:
The delay unit acts as an intermediary between the CRC signal and the alert signal generation. It processes the CRC signal by introducing a controlled time delay, thereby mediating the timing information to enable precise error detection. This intermediary component allows the system to maintain high measurement precision without requiring complex signal processing circuits.
3Productivity
If multiple CRC errors occur within 12 clock cycles, then data transmission speed is maintained, but the reliability of error detection deteriorates due to pulse overlap
Solution Approach 1:
The patent applies preliminary action by introducing a delay unit that processes the CRC signal before alert signal generation. The delay unit creates a time-shifted version of the CRC signal with a delay value greater than 12 clock cycles. This preliminary processing ensures that even when multiple errors occur within 12 clock cycles of each other, the delayed signals will be sufficiently separated in time to be identified as distinct errors, maintaining both high data transmission speed and high error detection reliability.
Data Source
AI summary
Provided are a memory device, including a cyclic redundancy check (CRC) circuit, configured to indicate whether a CRC error has been detected from data transmission between a host device and the memory device. The cyclic redundancy check (CRC) circuit includes: a detection module, configured to generate a CRC signal to correspondingly indicate that N CRC errors have been detected from the data transmission between the host device and the memory device, where the CRC signal has N pulses corresponding to the N CRC errors, and N is an integer greater than 1; and an alert signal generation unit, configured to generate an alert signal when a time interval between any two adjacent pulses in the CRC signal is less than or equal to a first preset time interval, where the alert signal has two pulses corresponding to the two adjacent pulses in the CRC signal.