CRC Generating Circuit for Parallel Memory Error Checking
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Solution Overview
Problem
Semiconductor memory devices face challenges in improving data reliability without compromising operating speed due to the time required for generating error detection codes.
Innovation Solution
A cyclic redundancy check code generating circuit that uses selecting signal generating units, selecting units, and adding units to generate CRC codes based on input/output mode information, allowing data and CRC codes to be output simultaneously without additional processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection code is generated to detect data error, then data reliability is improved, but operating speed is reduced
Solution Approach 1:
The patent applies preliminary action by generating the CRC check code in parallel with the data output process. The check code generating unit receives read data and generates the check code simultaneously as the data is being processed and output, rather than generating it after data output is complete. This preliminary parallel generation eliminates the additional time that would otherwise be required for error detection code generation, thereby maintaining operating speed while improving data reliability.
2Reliability
If CRC check code is generated using read data and control signals, then error detection capability is improved, but processing time is increased
Solution Approach 1:
The patent implements continuity of useful action by ensuring that the CRC check code generation process runs continuously and concurrently with the data read and output operations. The check code generating unit operates in parallel throughout the data processing cycle, utilizing the same read data and control signals (ordering information, bit structure information, burst length information) without interrupting or delaying the main data flow. This continuous parallel operation ensures that error detection capability is fully implemented while incurring no additional processing time penalty.
Data Source
AI summary
Disclosed are a semiconductor memory device, and a method of driving the same, and a cyclic redundancy check code generating circuit capable of performing cyclic redundancy check. A semiconductor memory device according to an aspect of the present invention includes a memory cell array, a data processing unit receiving data that is read from the memory cell array and selectively outputting at least some of the data according to ordering information, bit structure information, and burst length information, and a check code generating unit generating a cyclic redundancy check code to detect an error in the data being output, the check code generating unit generating and outputting the cyclic redundancy check code by using the read data, the ordering information, the bit structure information, and the burst length information.