CRC Generating Circuit for Real-Time Memory Error Detection
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Solution Overview
Problem
Semiconductor memory devices face challenges in improving data reliability without compromising operating speed, as existing error detection methods require time to generate and transmit error detection codes.
Innovation Solution
A cyclic redundancy check code generating circuit that uses selecting signal generating units, selecting units, and adding units to generate and output cyclic redundancy check codes based on data, ordering information, bit structure information, and burst length information, allowing for simultaneous data and check code output without additional processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection codes are generated and transmitted to detect data errors, then data reliability is improved, but operating speed is reduced
Solution Approach 1:
The patent generates cyclic redundancy check codes during the data read process itself, rather than after data retrieval. The check code generating unit operates concurrently with the data processing unit, performing error detection code generation as a preliminary action that does not add to the overall operation time, thus resolving the contradiction between reliability improvement and speed maintenance
2Reliability
If error detection codes are generated after data reading, then data integrity is ensured, but additional processing time is required
Solution Approach 1:
The patent merges the data processing function and check code generation function into a unified operational flow. The data processing unit and check code generating unit receive the same read data simultaneously and process it in parallel, combining what were previously separate sequential operations into concurrent processes, thereby ensuring data integrity without incurring additional processing time
Data Source
AI summary
Disclosed are a semiconductor memory device, and a method of driving the same, and a cyclic redundancy check code generating circuit capable of performing cyclic redundancy check. A semiconductor memory device according to an aspect of the present invention includes a memory cell array, a data processing unit receiving data that is read from the memory cell array and selectively outputting at least some of the data according to ordering information, bit structure information, and burst length information, and a check code generating unit generating a cyclic redundancy check code to detect an error in the data being output, the check code generating unit generating and outputting the cyclic redundancy check code by using the read data, the ordering information, the bit structure information, and the burst length information.