CRC Data Folding Circuit for Faster Error Detection
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Solution Overview
Problem
Existing data communication systems face challenges in optimizing CRC processing speed while maintaining efficient use of image processing systems in terms of area and power, and there is a need for improved error detection methods in data transmission between image sensors and processors.
Innovation Solution
A cyclic redundancy check (CRC) system and method that includes a data folding processing circuit with bit fold circuits and a stream fold circuit, along with a CRC processing circuit featuring flip-flops and CRC logic, to optimize CRC operations and enhance error detection efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional CRC processing is used in data transmission systems, then error detection capability is maintained, but CRC processing speed is limited and system complexity increases
Solution Approach 1:
The patent divides the CRC processing into two distinct modules: a data folding processing circuit that preprocesses input data by folding multiple data units into compact representations, and a CRC processing circuit that performs the actual cyclic redundancy check. This segmentation allows each module to be optimized independently, improving overall processing speed while managing complexity through functional separation.
Solution Approach 2:
The data folding processing circuit performs preliminary data transformation before the CRC operation. By folding multiple data units into compact representations in advance, the system reduces the amount of data that needs to be processed by the CRC logic, thereby accelerating the overall CRC processing speed without sacrificing error detection capability.
2Productivity
If optimized CRC operations are implemented to improve processing speed, then CRC processing speed increases, but area and power consumption of the image processing system may increase
Solution Approach 1:
The patent combines multiple data units into folded data representations, merging redundant information into compact forms. This merging reduces the overall data volume that must be processed by the CRC circuit, enabling faster processing with reduced chip area requirements compared to processing each data unit separately with full CRC logic.
Solution Approach 2:
The data folding processing circuit serves multiple functions: it preprocesses data for CRC operations, compresses data representation, and prepares folded data that can be efficiently processed by the CRC logic. This multi-functionality allows the system to achieve high processing speed without proportionally increasing chip area, as the same folding circuitry supports the accelerated CRC operation.
3Productivity
If data folding processing is applied to standardize unstructured data, then CRC operation efficiency improves, but device complexity increases
Solution Approach 1:
The patent segments the processing system into a dedicated data folding processing circuit and a CRC processing circuit. This segmentation isolates the complexity of data folding operations from the CRC logic, allowing each circuit to be designed and optimized independently. The folding circuit handles the complexity of standardizing unstructured data, while the CRC circuit focuses on efficient error detection.
Solution Approach 2:
The data folding processing circuit acts as an intermediary between the input data and the CRC processing circuit. It transforms unstructured input data into standardized folded data representations that are optimized for CRC operations, thereby improving CRC efficiency while containing complexity within the folding circuit rather than the CRC logic itself.
Data Source
AI summary
A cyclic redundancy check (CRC) system and a CRC method are provided. The CRC system includes a data folding processing circuit and a CRC processing circuit. The data folding processing circuit includes a first bit fold circuit configured to fold first input data into first fold data, a second bit fold circuit configured to fold second input data into second fold data, and a stream fold circuit configured to generate first fold streaming data based on the first fold data and the second fold data. The CRC processing circuit includes a first flip-flop configured to receive and store first dividend data of a first cycle, a second flip-flop configured to receive and store the first fold streaming data of the first cycle, and a CRC logic configured to perform a CRC operation on the first dividend data and the first fold streaming data.