CRC Engine Architecture for Wide-Vector Single-Cycle Processing
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Solution Overview
Problem
High-speed data communications face challenges in generating cyclic redundancy checks (CRC) within a single clock cycle due to increased clock frequencies, leading to timing constraints issues, especially with wide input data vectors and invalid bytes in the last block of data transmissions.
Innovation Solution
A high-bandwidth CRC engine is designed with a feed forward circuit and a feedback circuit, featuring an unfolded linear feedback shift register (LFSR) and a shifter circuit to handle wide input data vectors efficiently, using zero padding and a look-up table to align data for CRC calculation, ensuring timely CRC generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data rates for transmission increase, then communication speed is improved, but CRC generation speed becomes problematic
Solution Approach 1:
The CRC generation process is segmented into multiple parallel paths including a feed-forward path for initial CRC calculation and a feedback path for correction. The wide input data vector is divided into multiple blocks that are processed simultaneously through different circuit paths, enabling high-speed CRC generation that matches increased communication rates
Solution Approach 2:
The patent transitions from traditional serial CRC processing to a parallel processing architecture by adding spatial dimensions. Multiple CRC circuits operate simultaneously on different data blocks, and the feedback path adds a temporal dimension by correcting results from previous cycles, achieving CRC generation speed that keeps pace with high-data-rate transmissions
2Productivity
If wide input data vectors are processed, then data throughput is improved, but timing constraints become problematic
Solution Approach 1:
Wide input data vectors are segmented into multiple manageable blocks that are processed in parallel through separate CRC circuits. This segmentation reduces the critical path delay for each individual block while maintaining high overall throughput, preventing timing constraint violations even as data width increases
Solution Approach 2:
The feed-forward path performs preliminary CRC calculation on data blocks before the feedback path completes its correction process. This preliminary action allows the system to start processing subsequent blocks while previous blocks are being finalized, maintaining pipeline efficiency and meeting timing constraints for wide data vectors
3Productivity
If CRC generation is completed within a single clock cycle, then processing efficiency is improved, but circuit complexity increases
Solution Approach 1:
The single-clock-cycle CRC generation is achieved by segmenting the processing into parallel paths: a feed-forward path that computes initial CRC values and a feedback path that corrects them. Multiple smaller CRC circuits work simultaneously rather than one large sequential circuit, enabling single-cycle completion without excessive complexity in any single component
Solution Approach 2:
The feedback path provides correction values based on previous CRC results and feeds them forward to adjust the current computation. This feedback mechanism enables the circuit to handle variable-length data and alignment requirements while maintaining single-clock-cycle operation, achieving high processing efficiency with manageable complexity through iterative refinement
Data Source
AI summary
An apparatus and method therefor relate generally to a CRC engine. In such a CRC engine, a feed forward circuit is coupled to a feedback circuit. The feed forward circuit includes: an offset circuit configured to determine an offset value from header data; a look-up table circuit configured to select a seed value responsive to the offset value; a shifter circuit configured to successively load a zero padding and a payload in multiple byte blocks as aligned data with the zero padding leading the payload for a non-zero value of the offset value in a first of the multiple byte blocks having the zero padding and a first portion of the payload; and a CRC circuit configured to receive data zeroes to a seed port thereof and the aligned data to a data port thereof to provide an interim CRC value.