CRC-FEC Flit Encoding for Low-Latency Coherency Interconnects
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Solution Overview
Problem
As data rates for serial links exceed 32.0 GT/s, existing error correction mechanisms struggle to maintain low latency and high reliability in latency-critical coherency and memory interconnects, particularly in protocols like PCIe, CXL, and UPI, due to varying latency tolerances and bandwidth demands.
Innovation Solution
A common physical layer (PHY) design that supports multiple interconnect protocols, dynamically adjusting Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC) mechanisms based on protocol-specific performance needs, allowing for flexible flit sizes to optimize latency and bandwidth efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC) mechanisms are applied to ensure reliable data transmission at data rates exceeding 32.0 GT/s, then transmission reliability is improved, but transmission latency increases
Solution Approach 1:
The patent implements dynamic adjustment of FEC and CRC mechanisms based on protocol-specific latency tolerances and bandwidth demands. Different interconnect protocols (PCIe, CXL, UPI) can selectively enable or configure error correction mechanisms according to their specific requirements, allowing the system to optimize between reliability and latency dynamically rather than using a fixed configuration for all protocols
Solution Approach 2:
The patent applies different error correction mechanisms and configurations to different protocol types within the same physical layer. Latency-critical protocols can use simplified or optional error correction, while protocols with higher latency tolerance can employ more robust correction mechanisms. This localized customization allows each protocol to achieve optimal performance for its specific use case
2Adaptability or versatility
If a common physical layer (PHY) design supports multiple interconnect protocols with flexible flit sizes, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent designs a common physical layer (PHY) that can support multiple interconnect protocols (PCIe, CXL, UPI) through a unified architecture. This universal PHY implementation reduces the need for separate dedicated hardware for each protocol, thereby managing complexity while maintaining broad adaptability. The common PHY dynamically configures itself based on the active protocol, enabling multi-functionality without proportionally increasing device complexity
Data Source
AI summary
Systems, methods, and apparatuses can include transmission-side protocol stack circuitry comprising first cyclic redundancy check (CRC) circuitry to determine first CRC code for a first set of information and to determine second CRC code for a second set of information; and Flit encoding circuitry to encode a first portion of a Flit with the first set of information and the first CRC code, the Flit encoding circuitry to encode a second portion of the Flit with the second set of information and the second CRC code. Receiver-side protocol stack circuitry can include a low-latency path comprising first CRC check circuitry to perform a CRC check on a first portion of a received Flit. Receiver-side protocol stack circuitry can include a non-low-latency path comprising forward error correction (FEC) decoder circuitry to perform FEC on received Flits, and second CRC check circuitry to perform CRC check on received Flits that pass FEC.