CRC Frame Check Architecture for Variable-Width Data Blocks
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Solution Overview
Problem
Existing hardware implementations for cyclic redundancy check (CRC) computations in data communication systems inefficiently increase the gate count when processing variable numbers of input bytes, making them less effective for handling data blocks with varying widths.
Innovation Solution
A frame check sequence (FCS) module with a cyclic redundancy check (CRC) unit that uses an extended CRC transition matrix and matrix units to process data blocks of varying widths, allowing for efficient computation and error-checking by selecting the appropriate state vector based on the number of bytes and original width of the data block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing hardware implementations use fixed-width processing for CRC computations, then the computation logic is simplified, but the gate count increases inefficiently when handling variable number of input bytes
Solution Approach 1:
The patent implements dynamic processing by using a multiplexer to select between different processing paths based on the actual data width. The system can adaptively handle variable-width data blocks (1 to 32 bytes) by dynamically configuring the processing pipeline, rather than being fixed to a single width. This dynamic approach reduces gate count compared to supporting all possible widths with fixed logic.
Solution Approach 2:
The patent creates a universal CRC computation unit that can process multiple data widths (1-32 bytes) through a single unified architecture. The extended transition matrix and multiplexer-based selection mechanism allow one hardware unit to serve multiple functions, eliminating the need for separate fixed-width processing units for each possible data size.
2Adaptability or versatility
If hardware modules are designed to process variable number of bytes efficiently, then adaptability improves, but device complexity increases
Solution Approach 1:
The patent segments the CRC processing into distinct stages: data reception, padding to maximum width, extended transition matrix computation, and multiplexer-based selection. By dividing the processing into modular segments, the complexity is managed through structured organization rather than monolithic logic, making variable-width processing more efficient.
Solution Approach 2:
The patent introduces an intermediary padding mechanism that converts variable-width input data into a standardized maximum-width format before processing. This intermediary step simplifies the core computation by providing uniform input to the extended transition matrix, while the multiplexer acts as an intermediary to select the appropriate result based on original data width.
3Productivity
If fixed-width processing is used for CRC computations, then processing logic is simpler, but throughput efficiency decreases for variable-length data blocks
Solution Approach 1:
The patent implements periodic action by processing data in standardized clock cycles where each cycle handles a maximum-width block. The multiplexer selects the appropriate result based on the actual data width, enabling regular periodic processing while accommodating variable-length inputs. This periodic approach maximizes throughput by maintaining consistent processing rhythm.
Solution Approach 2:
The patent performs preliminary padding of variable-width data to maximum width before the main CRC computation. This preliminary action prepares the data in advance, allowing the core processing unit to operate at full throughput on standardized inputs, while the final result selection accounts for the original variable width.
Data Source
AI summary
Described embodiments provide for a frame check sequence (FCS) module with a cyclic redundancy check (CRC) unit that receives a data block (padded, if necessary, to a maximum width) and a first state vector and computes an internal vector based on an extended CRC transition matrix. The FCS module further includes a set of matrix units, each matrix unit configured to multiply the internal vector by a corresponding correction matrix wherein the multiplications result in a set of products. A multiplexer selects, by a control signal determined by a maximum number of bytes and the original width, a second state vector from the set of products.