CRC Generator Activation Logic for Multi-Width Parity Calculation
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Solution Overview
Problem
Conventional CRC generators for integrated circuits require substantial circuit resources and are slowed by a multiplexer boundary, making them inefficient in terms of logic usage and operational speed.
Innovation Solution
A cyclic redundancy check (CRC) generator design that eliminates the need for a multiplexer by using activation logic to dynamically enable and disable bits based on a width vector, allowing a single set of 32 equations to calculate parity for up to 16 different data widths, reducing the number of logic elements and enabling pipelining with fewer register stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate version of CRC logic is implemented for each data width with a multiplexer, then different data widths can be supported, but the circuit resources are substantially increased and the operation is slowed by the multiplexer boundary
Solution Approach 1:
The patent implements a single universal CRC logic unit that can handle multiple data widths (8-bit, 16-bit, 32-bit, 64-bit) through dynamic configuration of enable bits rather than requiring separate dedicated logic circuits for each width. This universal design reduces circuit resources while maintaining versatility across different data widths.
Solution Approach 2:
The patent uses dynamic enable bits that are activated or deactivated based on the selected data width, allowing the same hardware circuit to adapt its functionality in real-time. This dynamic configuration eliminates the need for static separate versions of CRC logic for each data width, reducing overall device complexity.
2Adaptability or versatility
If a separate version of CRC logic is implemented for each data width with a multiplexer, then different data widths can be supported, but the operation is slowed by the multiplexer boundary
Solution Approach 1:
The patent removes the multiplexer component entirely from the CRC generation process. Instead of using a multiplexer to select between different data width versions, the system directly activates the appropriate enable bits within a single unified logic unit, eliminating the speed bottleneck introduced by the multiplexer boundary.
Solution Approach 2:
The dynamic activation of enable bits allows the system to switch between different data widths without the overhead of multiplexer selection logic, thereby improving operational speed while maintaining the ability to support multiple data widths.
3Adaptability or versatility
If conventional CRC generator design is used, then multiple data widths can be accommodated, but the number of logic elements is substantially increased
Solution Approach 1:
The patent creates a single universal CRC logic unit that can accommodate multiple data widths (8-bit, 16-bit, 32-bit, 64-bit) through configurable enable bits, eliminating the need for multiple separate logic element sets. This universal approach substantially reduces the total quantity of logic elements required while maintaining full data width accommodation capability.
Solution Approach 2:
The patent merges multiple separate CRC logic versions into a single integrated logic unit by combining them shareably through enable bit control. This merging reduces the total number of logic elements from what would be required for separate implementations to a unified structure that serves all data widths.
Data Source
AI summary
A cyclic redundancy check (“CRC”) generator and method therefor are described. Checksum bits and checksum enable bits are bitwise ANDed to provide interim checksum outputs. The interim checksum outputs are XORed to provide resultant checksum outputs. Data bits and data enable bits are bitwise ANDed to provide interim data outputs. The interim data outputs are XORed to provide resultant data outputs. The resultant checksum outputs and the resultant data outputs are bitwise XORed to provide parity outputs.