CRC Interleaver Architecture for Low-Latency 5G NR Polar Encoding
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Solution Overview
Problem
Existing wireless communication systems face challenges in achieving high throughput and low latency, particularly in 5G NR, due to limitations in channel encoding processes such as CRC interleaving, polar encoding, and rate matching, which result in high hardware resource utilization and inefficient data transmission.
Innovation Solution
A flexible and parallelizable hardware architecture for channel encoding, including a CRC interleaver, polar encoder, and rate matcher, utilizing radix-k processing and FFT concepts, optimized for 5G NR, which reduces hardware resource usage while maintaining high throughput and low latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional channel encoding processes (CRC interleaving, polar encoding, rate matching) are used in 5G NR, then reliable data transmission is achieved, but hardware resource utilization becomes excessively high
Solution Approach 1:
The channel encoding process is divided into independent parallel stages: CRC attachment stage, polar encoding stage, and rate matching stage. Each stage processes data independently and can be implemented as separate hardware modules operating in parallel, reducing overall hardware resource requirements while maintaining encoding reliability
Solution Approach 2:
The patent transforms the sequential processing approach into a parallel processing architecture by utilizing time-multiplexed operations across different clock cycles. Data is processed through multiple encoding stages simultaneously in different time slots, effectively reducing hardware complexity while preserving the integrity of the encoding process
2Reliability
If conventional channel encoding processes are used, then error protection is provided, but transmission throughput is limited
Solution Approach 1:
CRC bits are attached to information bits before polar encoding begins, and rate matching patterns are pre-calculated based on code rate and block length parameters. This preliminary preparation enables the main encoding stages to operate at full speed without waiting for previous steps, thereby increasing throughput while maintaining error protection
Solution Approach 2:
The patent implements a continuous processing pipeline where CRC attachment, polar encoding, and rate matching operations overlap in time. While one data block is being encoded, the next block is being prepared, ensuring continuous useful action without idle cycles, thus maximizing transmission throughput
3Reliability
If conventional channel encoding processes are used, then data integrity is maintained, but processing latency is high
Solution Approach 1:
The encoding process is segmented into discrete parallel stages that can operate simultaneously on different data blocks. Each stage (CRC attachment, polar encoding, rate matching) processes its portion of the data independently and quickly, reducing the total time required while ensuring data integrity through systematic error protection at each stage
Solution Approach 2:
The patent employs periodic clock cycles to advance through different encoding stages in a rhythmic fashion. Each clock cycle advances the processing to the next stage or begins processing the next data block, creating a predictable and efficient processing rhythm that minimizes latency while maintaining data integrity
Data Source
AI summary
Example implementations include a method, apparatus and computer-readable medium of wireless communications, comprising receiving, at a cyclic redundance check (CRC) interleaver, a set of information bits in a message register. The implementations further include receiving a set of valid bits in a register; dividing the set of interleaved message bits and the set of interleaved mask bits into respective ones of a set of bit groups each with a same number of interleaved message bits and interleaved mask bits such that each set of bit groups includes a set of divided interleaved message bit groups and a set of divided interleaved mask bit groups; selecting valid bits based on the set of divided interleaved mask bit groups for each of the set of bit groups; and combining the valid bits to obtain a set of CRC interleaved information bits; and transmitting a polar encoded codeword on a control channel.