CRC Check Architecture for Low-Latency Parallel Decoding
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Solution Overview
Problem
Current methods for decoding convolutionally encoded telecommunications signals face challenges in efficiency, power consumption, and latency, particularly in mobile systems, due to high decoding complexity and simultaneous read/write access requirements in register exchange processes, and increased latency in trace-back approaches.
Innovation Solution
The proposed solution involves parallel processing of trellis searches, trace-forward, and trace-back operations using multiple dedicated memory registers and multiplexers, allowing for simultaneous storage and output of decision bits in various registers and memories, and implementing tail-biting checks to optimize memory usage and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If register exchange methods are used for Viterbi decoding, then decoding capability is achieved, but power consumption increases and battery life decreases
Solution Approach 1:
The patent segments the L×N register array into multiple smaller register arrays that can be accessed in parallel. This segmentation allows the decoding process to be distributed across multiple smaller memory structures, reducing the power consumption associated with simultaneous access to a single large register array while maintaining the required decoding capability.
Solution Approach 2:
The patent implements dynamic access patterns to the register arrays, where different subsets of registers are accessed at different time steps rather than all registers simultaneously. This dynamic approach reduces peak power consumption by spreading the access load over time while still achieving the required decoding functionality.
2Quantity of substance
If trace-back approach is used for decoding, then memory usage is reduced, but latency increases
Solution Approach 1:
The patent performs preliminary actions by maintaining and updating survivor path information in the segmented register arrays during the forward pass. This preliminary preparation of path information allows the trace-back process to proceed more efficiently with reduced latency, as the necessary path data is already organized and accessible when needed.
Solution Approach 2:
The patent introduces a temporal dimension to the memory structure by organizing registers in a time-varying manner across multiple time steps. This allows the system to achieve both reduced memory usage and reduced latency by accessing the appropriate time-step registers during the trace-back process, rather than requiring all memory to be available simultaneously.
3Productivity
If simultaneous read and write access to all registers is required, then decoding is performed, but power consumption requirements increase
Solution Approach 1:
The patent divides the register array into multiple segments that can be accessed independently and in parallel. This segmentation allows simultaneous read and write operations to be distributed across multiple smaller register subsets, maintaining high decoding throughput while reducing the power consumption associated with accessing a single large register array simultaneously.
Solution Approach 2:
The patent designs the segmented register arrays and associated multiplexers to perform multiple functions - serving both as storage for survivor paths and as accessible memory during both forward and backward passes. This multi-functionality allows the system to maintain high productivity while reducing peak power requirements by reusing the same physical structures for multiple purposes.
Data Source
AI summary
The present disclosure describes a method, performed by a data processor comprising a cyclic redundancy check (CRC) module configured for calculating CRC remainders for encoded data and a comparator comprising a shift register, for making a cyclic redundancy check of an encoded data record of bit length L, in which at least A bits of the record represent content data and at least B bits represent check data. A system for performing a cyclic redundancy check is also described.