CRC-RAID Memory System with Dynamic Parity Deferral
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Solution Overview
Problem
Current DRAM technologies face significant challenges in achieving reliable error correction and detection with high power efficiency, as existing solutions like chipkill require excessive chip access and result in high power consumption and cost due to redundancy overhead.
Innovation Solution
The implementation of a CRC-RAID system architecture in a CXL memory system, which uses a single RAID parity chip to reconstruct data and reduce overhead, allowing for efficient error detection and correction with reduced power consumption by deferring parity calculations during high memory traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chipkill error correction scheme is used, then reliability is improved, but power consumption increases due to excessive chip access
Solution Approach 1:
The patent segments the error correction function into two distinct modes: instant write mode for low-traffic periods where parity is updated immediately with full chip access, and delayed write mode for high-traffic periods where parity updates are deferred. This segmentation allows the system to achieve both high reliability and low power consumption at different times, resolving the contradiction between continuous error correction and power savings.
Solution Approach 2:
The patent implements dynamic switching between instant write and delayed write modes based on real-time memory traffic conditions. The controller monitors traffic intensity and dynamically adjusts the parity update strategy, transitioning from immediate updates (high power, high reliability) to deferred updates (low power, maintained reliability through periodic synchronization). This dynamic adaptation resolves the contradiction by optimizing the balance between power consumption and error correction based on operational context.
2Ease of manufacture
If redundant array of inexpensive disks (RAID) is used, then cost is reduced, but power consumption increases due to multiple chip accesses for parity calculation
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing parity information during low-traffic periods when power consumption is less critical. The parity data is prepared in advance and stored in buffer memory, so that during high-traffic periods, the system can retrieve pre-computed parity without performing energy-intensive real-time calculations across multiple chips. This resolves the contradiction by performing the costly RAID parity operations when they least impact power consumption.
Solution Approach 2:
The patent creates copies of parity information and stores them in buffer memory during instant write mode. These parity copies are then retrieved during delayed write mode operations, eliminating the need for repeated real-time parity calculations across multiple memory chips. By copying and caching parity data, the system reduces the computational overhead and chip access requirements during high-traffic periods, thereby reducing power consumption while maintaining the cost-effective RAID architecture.
3Reliability
If instant parity update is performed, then data integrity is improved, but memory traffic performance deteriorates due to additional access overhead
Solution Approach 1:
The patent dynamically adjusts the parity update strategy based on memory traffic conditions. During low-traffic periods, instant parity updates are performed to ensure high data integrity. During high-traffic periods, the system switches to delayed write mode where parity updates are deferred, allowing memory operations to proceed at full speed without the overhead of immediate parity calculations. This dynamic switching resolves the contradiction by optimizing the balance between data integrity and performance based on real-time traffic conditions.
Solution Approach 2:
The patent implements periodic parity synchronization in delayed write mode, where parity information is updated at scheduled intervals rather than continuously. This periodic action maintains data integrity over time while allowing high-speed memory operations to proceed uninterrupted between synchronization points. The periodic parity updates ensure that even though individual writes may be delayed, the overall system maintains data consistency without continuously impacting memory traffic performance.
Data Source
AI summary
Provided is a memory system comprising a plurality of memory channels each having a parity bit, a redundant array of independent devices (RAID) parity channel, and a controller of the memory system. The controller is configured to receive a block of data for storage in the memory channels and determine at least one of (i) when a data traffic demand on the memory channels is high and (ii) when a data traffic demand on the memory channels is low. Upon determining the data traffic demand is low, writing the block of data for storage in the memory channels and concurrently updating the parity bits and the RAID parity channel for the stored block of data. Upon determining the data traffic demand is high, only writing the data for storage in the memory channels.