Cyclic Redundancy Check Retry for CXL Memory Link Errors
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Solution Overview
Problem
Existing memory systems in CRC-RAID environments face challenges in ensuring high reliability and accuracy during read and write operations due to errors in the link between the controller and memory, which can lead to inefficiencies and increased latency.
Innovation Solution
Implementing a dynamic link exchange protocol (DLEP) in LP5 components within the CXL devices, utilizing CRC engines for retry operations to detect and correct errors, thereby avoiding the need for RAID recovery and improving data transmission reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CRC retry operations are implemented in the link between controller and memory, then reliability and accuracy of data transmission are improved, but device complexity increases due to additional CRC engines and retry logic
Solution Approach 1:
The patent implements preliminary error detection by attaching CRC checkers to both the controller and memory components. These checkers are prepared in advance to detect link errors before they propagate, enabling proactive retry operations rather than reactive error handling. The CRC engines are pre-configured with generation and verification capabilities to intercept and correct errors at the link level.
Solution Approach 2:
The patent introduces CRC engines as intermediary components between the controller and memory components. These intermediaries perform error detection and triggering of retry operations without requiring full RAID recovery involvement. The CRC checker acts as a mediator that intercepts erroneous transmissions and initiates localized retry sequences, isolating the error handling from the broader RAID system.
2Reliability
If RAID recovery mechanisms are invoked for link errors, then data integrity is maintained, but latency increases due to the overhead of full RAID recovery procedures
Solution Approach 1:
The patent extracts the error detection and retry triggering functionality from the full RAID recovery mechanism and places it directly at the link level within memory components. By taking out the CRC checker and retry logic from the centralized RAID recovery path and embedding them in the link layer, the system handles common link errors locally without invoking the overhead of complete RAID recovery procedures.
Solution Approach 2:
The patent applies partial action by implementing error handling that is sufficient for link-level errors without the full extent of RAID recovery. The CRC-based retry mechanism provides just enough error correction capability at the link level to handle transmission errors, avoiding the excessive action of invoking complete RAID recovery for errors that can be resolved through simpler retry operations.
3Device complexity
If link errors are not corrected at the memory component level, then device complexity is reduced, but productivity decreases due to repeated failed operations and higher latency
Solution Approach 1:
The patent enables memory components to self-correct link errors through integrated CRC checkers and retry logic. When a link error is detected, the memory component autonomously triggers a retry operation without requiring external intervention from the controller or RAID recovery mechanisms. This self-service capability allows the system to maintain high productivity by quickly recovering from transient link errors without involving higher-level error handling systems.
Data Source
AI summary
Provided is a computing system including a memory system in communication with a host, and for storing data therein and the memory system includes a memory having a plurality of memory components and a memory array and coupled to the controller via a memory interface. Each memory component includes a memory cyclic-redundancy-check (CRC) engine that performs a CRC check of data during read and write operations between the host and the memory array. The memory system also includes a controller that has a plurality of controller CRC engines and communicates with the memory components to control data transmission between the memory, the host and the memory array.