Four-Bit CRC Sequence With Hamming Distance Two For Wireless Signal Fields
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Solution Overview
Problem
The existing 802.11ah specification's four-bit cyclic redundancy check (CRC) sequence has a Hamming distance of 1, which does not guarantee detection of single-bit errors in the signal field, posing a challenge for reliable error detection in wireless communications.
Innovation Solution
A new preamble structure with a four-bit CRC sequence is introduced, providing a Hamming distance of two, generated using a generator polynomial of x^4 + x + 1 or by concatenating four one-bit CRCs, ensuring detection of single-bit errors in the signal field, and implemented in the IEEE 802.11ah specification for wireless communication systems operating in 1GHz and lower frequency bands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a four-bit CRC sequence with Hamming distance of 1 is used (as in the original 802.11ah specification), then the implementation is simple and lightweight, but single-bit errors cannot be reliably detected
Solution Approach 1:
The patent changes the Hamming distance parameter of the CRC sequence from 1 to 2 by using a specific generator polynomial (x^4 + x + 1), thereby improving error detection capability while maintaining the same CRC length and basic structure
Solution Approach 2:
The patent presents an alternative approach of concatenating four one-bit CRCs (parity bits) to achieve the same Hamming distance of 2, dividing the error detection function into separate parity check components that can be independently calculated and combined
2Reliability
If a more robust error detection mechanism is implemented, then the reliability of wireless communication improves, but the processing overhead and complexity increase
Solution Approach 1:
The patent uses a four-bit CRC sequence which provides partial error detection capability (Hamming distance of 2 detects all single-bit errors) without implementing a full-length CRC that would provide complete error detection but require significantly more processing time and resources
Solution Approach 2:
By optimizing the generator polynomial to x^4 + x + 1, the patent achieves maximum error detection efficiency for a four-bit CRC, ensuring that the limited processing resources are used most effectively to detect single-bit errors
Data Source
Figure 1
Figure 1A~1C
Figure 1D~1F
AI summary
According to various aspects of the present disclosure, medium access control (MAC) sublayer logic of a device or a system may generate and implement a preamble structure of a data unit including a signal field which includes a four-bit cyclic redundancy check sequence providing a Hamming distance of two. The signal field portion of the preamble structure may include information related to a plurality of physical layer parameters used for wireless communication of the data unit. The preamble structure may be stored on a machine-accessible medium. The preamble may be generated by a data unit builder of the device, which may further receive a frame including a data payload, and encapsulate the frame with the preamble portion to generate the data unit. A transmitter coupled with the data unit builder may then wirelessly transmit the data unit using an antenna array.