CRC Syndrome Error Correction for Lightly Corrupted Packets

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Solution Overview

Problem

Current systems for managing errors in cyclic redundancy checks (CRCs) in wireless communications often discard entire packets with minor errors, leading to loss of valuable information and inefficient communication quality, especially in real-time applications like video transmission, and existing error correction methods are either time-consuming or require significant memory.

Innovation Solution

A computer-implemented method that generates a list of potential error vectors by forcing and canceling bits using a generator polynomial, allowing for the correction of data packets with errors while maintaining the equivalence relationship with the original syndrome, either through explicit arithmetic operations or implicit table representation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If CRC error detection is used to ensure data integrity, then reliability is improved, but packets with minor errors are discarded leading to loss of valuable information

Engineering Contradiction:
Improvedata integrityVSAvoidpacket loss
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent changes the parameter of error handling from binary (discard/accept) to multi-state (correctable error patterns identification). By analyzing the CRC syndrome to identify specific error patterns rather than simply detecting errors, the system can distinguish between correctable and uncorrectable errors, thereby reducing packet loss while maintaining data integrity through selective correction.

Inventive Principle:
Principle #35Parameter changes

2Loss of information

If exhaustive error correction methods are used to correct packets, then packet loss is reduced, but time-consuming calculations and significant memory are required

Engineering Contradiction:
Improvepacket lossVSAvoidcalculation time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The patent applies partial action by implementing error correction only for specific correctable error patterns identified through CRC syndrome analysis, rather than attempting to correct all possible errors. This selective approach reduces computational time and memory requirements while still achieving the goal of reducing packet loss for correctable errors.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent segments the error correction process into distinct stages: CRC syndrome calculation, error pattern identification based on syndrome values, and selective correction. This segmentation allows the system to efficiently handle only the necessary correction operations without performing exhaustive analysis on all packets, thereby reducing overall computational burden.

Inventive Principle:
Principle #1Segmentation

3Reliability

If traditional CRC error detection is used, then data integrity is maintained through packet discarding, but communication quality deteriorates due to significant packet loss

Engineering Contradiction:
Improvedata integrityVSAvoidcommunication quality
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent converts the harmful effect of CRC error detection (which normally leads to packet discarding) into a beneficial tool for error correction. By analyzing the CRC syndrome patterns, the system identifies specific error locations and corrects them, transforming what was previously a source of packet loss into a mechanism for improving communication quality through selective correction.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS11784664B2Methods and systems for bit error determination and correction
Publication Date: 2023.10.10 ECOLE DE TECH SUPERIEURE
  • US11784664B2 patent drawing
  • US11784664B2 patent drawing
  • US11784664B2 patent drawing

AI summary

A computer-implemented technique for correcting a data packet having a payload and cyclic redundancy check information provides a list of possible packet errors by algorithmic operations of forcing and cancelling bits at certain positions using a generator polynomial, while maintaining the equivalence relationship with the original syndrome, performed explicitly using arithmetic operations or implicitly using a table representative of such arithmetic operations. Correction can then be implemented using an error chosen from the list.