CRC Error Detection Circuit Using a Unified Generation Matrix
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As DRAMs shrink in size, bit errors in memory cells increase, leading to decreased yield and operational efficiency in semiconductor memory devices.
Innovation Solution
An error detection code generation circuit is implemented, comprising a first and second CRC engine and an output selection engine, using the same generation matrix to generate and merge error detection code bits based on unit data and DBI bits, with the mode signal indicating code rate mode, to detect errors in main data transmitted to semiconductor memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate generation matrices are used for different code rate modes, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent employs a single generation matrix that serves multiple code rate modes (1/2, 2/3, 3/4, 7/8) through configurable selection logic. The same matrix structure is reused across different operating modes by selectively enabling specific rows or columns based on the desired code rate, eliminating the need for separate generation matrices for each mode and thereby reducing hardware overhead while maintaining error detection capability.
2Reliability
If multiple CRC engines are used for different code rate modes, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple CRC engine functionalities into a single unified CRC engine. By integrating the generation matrix selection logic and output merging mechanisms within one engine, the circuit structure is simplified compared to having separate CRC engines for each code rate mode. The unified engine selectively processes data according to the required code rate and merges outputs appropriately, reducing overall circuit complexity.
3Measurement precision
If DBI bits are processed separately for each unit data, then error detection precision is improved, but processing time increases
Solution Approach 1:
The patent implements continuous processing of DBI bits and unit data through a streamlined generation matrix structure. The matrix is designed to process multiple units of data and their corresponding DBI bits in a continuous manner without requiring separate processing stages for each unit, thereby maintaining high error detection precision while minimizing processing time through efficient parallel operations.
Data Source
AI summary
An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.