CRC Logic Virtual Stuff Bit Insertion for CAN FD Synchronization
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Solution Overview
Problem
The existing CRC methods for CAN FD frames are flawed, particularly when the identifier starts with four dominant bits, leading to incorrect interpretation of the Start of Frame bit, resulting in undetected bit errors and synchronization issues, which affect the reliability of data transmission in CAN and CAN FD bus systems.
Innovation Solution
A method is introduced where stuff bits are inserted into frames according to a predetermined rule, and an additional evaluation step is performed by the CRC calculation logic to insert a value '1' if the CRC checksum is '0...0', ensuring reliable detection of bit errors and maintaining synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stuff bits are inserted according to predetermined rule to prevent misinterpretation of bit sequences, then synchronization reliability is improved, but CRC calculation accuracy deteriorates when identifier starts with four dominant bits
Solution Approach 1:
The transmitter performs preliminary action by inserting a virtual stuff bit into the CRC calculation before transmitting the frame. This virtual stuff bit is accounted for in the CRC computation at the transmitter side, ensuring that the receiver can accurately verify the CRC even when actual stuff bits are inserted due to five consecutive dominant bits in the identifier field.
Solution Approach 2:
The invention changes the parameter handling by introducing a conditional adjustment mechanism. When the identifier starts with four dominant bits (triggering stuff bit insertion), the system adjusts the CRC calculation by accounting for the virtual stuff bit. This parameter change ensures that the CRC polynomial calculation remains accurate despite the insertion of actual stuff bits during transmission.
2Ease of operation
If the Start of Frame bit is overwritten with a recessive bit in the receiver, then the receiver interprets the frame correctly, but bit error detection fails for identifiers beginning with four dominant bits
Solution Approach 1:
The invention implements feedback through the CRC verification mechanism. The transmitter calculates the CRC including the virtual stuff bit and sends it with the frame. The receiver uses this CRC value to verify the received frame, providing feedback that detects whether bit errors occurred during transmission, thereby maintaining reliability despite the Start of Frame bit overwriting.
3Device complexity
If CRC initialization vector is set to '00000000000000000' for CAN FD frames, then CRC calculation is simplified, but the first leading '0' bit is not sensed by the CRC test
Solution Approach 1:
The transmitter performs preliminary action by pre-calculating the CRC value including the effect of the virtual stuff bit before transmission. This allows the receiver to use the simple initialization vector '00000000000000000' while still achieving accurate bit error detection, as the virtual stuff bit's effect is already embedded in the transmitted CRC value.
Data Source
AI summary
The disclosure relates to a method for serially transmitting a frame from a transmitter to at least one receiver via a bus line, as well as a subscriber station for a bus system. According to said method, stuff bits for generating additional signal edges are inserted into the frame by the transmitter according to a predetermined rule, and the stuff bits are removed again by the receiver when evaluating a received frame, a CRC calculation logic of a CRC generator calculating a CRC checksum that is comprised by said frame, and a value of “1” being inserted into said CRC calculation logic in an additional evaluation step if a value of “0 . . . 0” has been determined for the CRC checksum in the running calculation executed by the CRC calculation logic.