Credential Allocator Circuit for Multi-Peripheral Address Translation
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Solution Overview
Problem
The complexity of address translations across multiple address spaces in modern computer systems, particularly due to the presence of multiple microprocessors and PCIe interfaces, complicates system design and increases processing overhead.
Innovation Solution
A system that includes a credential allocator circuit to generate unique identification values for channels and peripherals, and mapping circuitry to map these identification values to corresponding function values, traffic class values, and address space values, thereby simplifying address translations and improving system efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple microprocessors and PCIe interfaces are used to improve processing capabilities, then system functionality and performance are enhanced, but address space complexity and translation overhead increase
Solution Approach 1:
The patent introduces an address translation mechanism that acts as an intermediary between multiple microprocessors/PCIe interfaces and the memory system. This translator component mediates address translations, managing multiple address spaces without requiring extensive translations at each step, thereby reducing overall system complexity while maintaining enhanced processing capabilities
Solution Approach 2:
The address translation mechanism is designed to handle multiple address spaces from different microprocessors and PCIe interfaces through a universal translation framework. This multi-functional approach allows a single translation system to manage diverse address spaces, reducing the need for separate translation mechanisms for each component
2Adaptability or versatility
If address translations are performed at each step and in each direction to manage multiple address spaces, then address space management is achieved, but system design complexity and processing overhead increase
Solution Approach 1:
The patent implements preliminary address translation where addresses are translated in advance before being passed through the system. This preliminary action allows address spaces to be managed efficiently without requiring translations at each subsequent step, reducing both design complexity and processing overhead while maintaining versatile address space management
3Measurement precision
If extensive address translations are performed to route requests across multiple address spaces, then request routing accuracy is improved, but processing time and system performance decrease
Solution Approach 1:
The patent extracts the address translation function into a dedicated translator component that handles translations efficiently in a centralized manner. By separating this function from the request processing path, the system achieves accurate request routing across multiple address spaces without the performance penalty of extensive translations at each processing step
Data Source
AI summary
System and methods are provided. An example system includes multiple peripherals including a first peripheral and a second peripheral, in which the first peripheral is associated with a first channel and a second channel; and a credential allocator circuit to generate a unique identification value for each of the first channel, the second channel and the second peripheral. The system further includes mapping circuitry to map a first function of the system to the first channel, map a second function of the system to the second channel, and map a third function of the system to the second peripheral; map each identification value generated by the credential allocator circuit to a corresponding function value and a corresponding traffic class value; and map each identification value generated by the credential allocator circuit to a corresponding address space value. A firewall of the system is initialized to recognize the identification values generated by the credential allocator circuit.