Credit-Based Arbiter Thresholds for Coherent Shared Memory Access

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Solution Overview

Problem

Multi-core systems face coherency issues due to simultaneous access to shared memory, leading to operational inefficiencies and potential outdated data retrieval, particularly when software cache maintenance operations are slow or resource-intensive.

Innovation Solution

A multi-core shared memory controller (MSMC) is implemented with a snoop filter bank, cache tag bank, and memory bank, which includes coherent slave interfaces, an external memory master interface, and an arbiter circuit to manage memory access requests, determine snoop requests, and allocate virtual channels, ensuring coherent data access and efficient arbitration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If software cache maintenance operations are used to manage coherency, then coherency can be maintained, but operational efficiency deteriorates due to slow performance and excessive operational time consumption

Engineering Contradiction:
ImprovecoherencyVSAvoidoperational efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent replaces software-based cache maintenance operations with a hardware-based coherency management system. The snoop filter bank, cache tag bank, and arbiter circuit operate in hardware to automatically manage cache coherency across multiple cores, eliminating the performance overhead of software intervention while maintaining coherency reliability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces a hardware intermediary layer consisting of the snoop filter bank and cache tag bank that mediates between memory access requests and cache operations. This intermediary automatically tracks cache states and manages coherency without requiring software intervention, thus improving operational efficiency while maintaining coherency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If hardware-based coherency management is implemented, then operational efficiency improves, but device complexity increases due to additional components

Engineering Contradiction:
Improveoperational efficiencyVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the coherency management functionality into distinct modular components: snoop filter bank, cache tag bank, and arbiter circuit. Each component has a specific function and can be independently implemented and optimized, which manages device complexity while achieving efficient hardware-based coherency management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent designs the snoop filter bank and cache tag bank to serve multiple functions: tracking cache states, managing coherency, and enabling efficient arbitration. This multi-functionality reduces the need for separate dedicated components, thereby managing device complexity while maintaining operational efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If credit-based arbitration is used to manage memory access, then resource allocation efficiency improves, but device complexity increases due to credit threshold management

Engineering Contradiction:
Improveresource allocation efficiencyVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a self-service credit-based arbitration system where the arbiter circuit automatically manages credit allocation and threshold monitoring without external intervention. The system autonomously makes arbitration decisions based on credit thresholds, improving resource allocation efficiency while containing device complexity through automated management.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent employs dynamic credit threshold adjustment in the arbitration mechanism. The arbiter circuit adapts credit allocation based on system conditions and memory access patterns, allowing efficient resource allocation while managing complexity through adaptive rather than static control.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11429527B2Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure
Publication Date: 2022.08.30 TEXAS INSTRUMENTS INC
  • US11429527B2 patent drawing
  • US11429527B2 patent drawing
  • US11429527B2 patent drawing

AI summary

A device includes an arbiter circuit configured to receive a first request for a resource. The first request is associated with a first credit cost. The arbiter circuit is further configured to receive a second request for the resource. The second request is associated with a second credit cost. The arbiter circuit is further configured to select the first request for the resource as an arbitration winner. The arbiter circuit is further configured to decrement a number of available credits associated with the resource by the first credit cost. The arbiter circuit is further configured to, in response to the number of available credits associated with the resource falling to a lower credit threshold, wait until the number of available credits associated with the resource reaches an upper credit threshold to select an additional arbitration winner for the resource.