Credit-Based Arbiter Thresholds for Multi-Level Resource Arbitration
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Solution Overview
Problem
Multi-core systems face coherency issues due to simultaneous access to shared memory, leading to operational inefficiencies and outdated data, particularly when software cache maintenance operations are slow or resource-intensive.
Innovation Solution
A multi-core shared memory controller (MSMC) with a snoop filter bank, cache tag bank, and memory bank is implemented, which includes coherent slave interfaces and an external memory master interface, allowing for efficient management of memory access requests and coherency through hardware-based snoop filtering and cache tag management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software cache maintenance operations are used to manage coherency, then data coherence can be maintained, but operational efficiency deteriorates due to slow performance and excessive operational time consumption
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based snoop filter system. The snoop filter bank is implemented in hardware within the memory controller, using dedicated circuits to automatically track and manage cache coherency states. This hardware implementation eliminates the performance overhead of software intervention while maintaining reliable data coherence across multiple processor cores.
2Productivity
If hardware-based snoop filtering is implemented, then operational efficiency improves, but device complexity increases due to additional hardware components
Solution Approach 1:
The patent integrates the snoop filter bank directly into the memory controller structure, merging the coherency management function with the existing memory access control logic. The snoop filter bank shares the same physical infrastructure as the cache tag bank and memory interface, consolidating multiple functions into a unified hardware architecture rather than adding separate standalone components.
Solution Approach 2:
The snoop filter bank is designed to handle multiple coherency management tasks simultaneously, including tracking cache states, generating snoop requests, and managing invalidate operations across different cache levels. This multi-functional design allows a single hardware structure to perform various coherency maintenance operations, reducing the need for additional specialized components.
3Productivity
If multiple processor cores access shared memory simultaneously, then processing capability improves, but coherency issues arise leading to outdated data
Solution Approach 1:
The snoop filter system continuously monitors memory access patterns and cache states, providing real-time feedback to the memory controller. When a cache miss or invalidation condition is detected, the system automatically generates appropriate snoop requests to other cores' caches, ensuring that all processors have access to the most current data. This closed-loop feedback mechanism maintains data coherence without requiring manual intervention or complex software protocols.
Data Source
AI summary
A device includes an arbiter circuit configured to receive a first request for a resource. The first request is associated with a first credit cost. The arbiter circuit is further configured to receive a second request for the resource. The second request is associated with a second credit cost. The arbiter circuit is further configured to select the first request for the resource as an arbitration winner. The arbiter circuit is further configured to decrement a number of available credits associated with the resource by the first credit cost. The arbiter circuit is further configured to, in response to the number of available credits associated with the resource falling to a lower credit threshold, wait until the number of available credits associated with the resource reaches an upper credit threshold to select an additional arbitration winner for the resource.