Credit-Aware Central Arbitration for Multi-Core Memory Coherency
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Solution Overview
Problem
Multi-core systems face coherency issues due to multiple processing cores accessing shared memory addresses, leading to inefficiencies and operational delays, particularly in software-based cache maintenance operations.
Innovation Solution
A multi-core shared memory controller (MSMC) with a snoop filter bank, cache tag bank, and memory bank, utilizing hardware-based coherency control to manage cache coherency and reduce operational inefficiencies by minimizing unnecessary snoop requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based cache maintenance operations are used to manage coherency, then coherency can be maintained, but operational efficiency deteriorates (slow operations, excessive operational time)
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency controller that automatically manages cache coherency. The coherency controller includes a snoop filter bank and cache tag bank that operate in hardware to detect and resolve coherency issues without requiring software intervention, thereby maintaining reliability while dramatically improving operational efficiency.
Solution Approach 2:
The coherency controller is designed to autonomously manage cache coherency without external software control. It automatically monitors cache states, detects coherency violations, and resolves them through hardware-based snoop requests and cache line invalidation, enabling the system to self-regulate coherency without consuming software operational time.
2Productivity
If hardware-based coherency control is implemented, then operational efficiency improves, but device complexity increases
Solution Approach 1:
The coherency controller is segmented into distinct functional units: a snoop filter bank for tracking cache states, a cache tag bank for storing tag information, and a control logic unit for coordinating operations. This segmentation allows each component to perform its specific function efficiently while keeping the overall design manageable and modular.
Solution Approach 2:
The coherency controller is designed to handle multiple cache coherency protocols and operations through a unified hardware architecture. The snoop filter bank and cache tag bank can service multiple cache lines and support various coherency scenarios (read misses, write misses, invalidate requests) through a single versatile structure, reducing overall device complexity compared to dedicated hardware for each scenario.
3Productivity
If multiple processing cores access shared memory addresses simultaneously, then system throughput increases, but coherency issues arise leading to operational delays
Solution Approach 1:
The snoop filter bank pre-tracks the state of cache lines before coherency issues arise. By maintaining snoop filter entries that record which cores have cached copies of memory lines, the system can proactively identify potential coherency conflicts and resolve them before they cause operational delays, enabling multiple cores to access shared memory addresses simultaneously without time loss.
Solution Approach 2:
The coherency controller implements a feedback mechanism where the cache tag bank continuously monitors cache states and provides information back to the control logic. When a coherency violation is detected through snoop requests, the controller immediately responds by invalidating or updating the appropriate cache lines, creating a closed-loop system that eliminates coherency delays while maintaining high system throughput.
Data Source
AI summary
A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.