Credit-Aware Memory Arbitration for Multi-Core Coherency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multi-core systems face coherency issues due to multiple processing cores accessing shared memory addresses, leading to operational inefficiencies and outdated data retrieval, especially when software cache maintenance operations are slow or resource-intensive.
Innovation Solution
Implementing a multi-core shared memory controller (MSMC) with a snoop filter bank, cache tag bank, and memory bank, along with an arbitration and data path manager to enforce coherency and manage memory access requests, utilizing hardware-based coherency controllers and virtual channels to reduce component count and clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software cache maintenance operations are used to ensure coherency, then data coherency is maintained, but operational efficiency deteriorates due to slow performance and excessive operational time
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency controller that automatically monitors and manages cache coherency. The coherency controller includes a snoop filter bank and cache tag bank that operate in hardware to detect and resolve coherency issues without requiring software intervention, thereby maintaining data coherency while significantly improving operational efficiency and reducing performance overhead
Solution Approach 2:
The coherency controller implements self-service by automatically detecting cache coherency violations and initiating appropriate maintenance operations without external software control. The snoop filter bank autonomously monitors memory access requests and the cache tag bank automatically invalidates or updates cache entries as needed, enabling the system to maintain coherency independently without consuming processor resources for software management
2Productivity
If multiple processing cores access shared memory addresses simultaneously, then processing parallelism is improved, but coherency management complexity increases
Solution Approach 1:
The patent introduces a coherency controller as an intermediary component between multiple processing cores and shared memory. This controller acts as a mediator that intercepts memory access requests, monitors cache states, and coordinates coherency maintenance across all cores. The snoop filter bank and cache tag bank within the controller track memory access patterns and automatically manage coherency, thereby enabling high processing parallelism while keeping coherency management complexity centralized and automated rather than distributed across multiple cores
3Productivity
If hardware-based coherency controllers are implemented, then operational efficiency is improved, but device complexity and component footprint increase
Solution Approach 1:
The patent merges the coherency controller functionality directly into the memory controller unit, combining what could be separate components into a single integrated structure. The snoop filter bank, cache tag bank, and coherency management logic are all integrated within the memory controller, eliminating the need for separate hardware coherency management components. This integration maintains the operational efficiency benefits of hardware-based coherency control while reducing the overall device complexity and component footprint
Data Source
AI summary
A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.