Virtual Network Pre-Arbitration for Credit-Based Memory Access
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Solution Overview
Problem
Multi-core systems face coherency issues due to simultaneous access to shared memory, leading to operational inefficiencies and potential outdated data retrieval, especially when software cache maintenance operations are slow or resource-intensive.
Innovation Solution
A multi-core shared memory controller (MSMC) with a snoop filter bank, cache tag bank, and memory bank is implemented, which includes coherent slave interfaces, an external memory master interface, and an arbiter circuit to manage memory access requests and determine snoop requests based on cache hit status and snoop filter states, ensuring coherent data access across processor packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software cache maintenance operations are used to manage coherency, then coherency can be maintained, but operational efficiency deteriorates due to slow performance and excessive operational time consumption
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency monitoring system. The snoop filter bank and cache tag bank are hardware structures that automatically monitor and enforce cache coherency through circuit-level operations, eliminating the performance overhead of software intervention while maintaining coherency guarantees across multi-core systems.
Solution Approach 2:
The patent introduces a hardware intermediary layer consisting of the snoop filter bank and cache tag bank that mediates between cache memory and main memory. This intermediary automatically intercepts and monitors memory access requests, enforcing coherency protocols at the hardware level without requiring software cache maintenance operations, thus improving operational efficiency while preserving coherency.
2Productivity
If hardware-based coherency management is implemented, then operational efficiency is improved, but device complexity increases due to additional components
Solution Approach 1:
The patent merges the snoop filter bank and cache tag bank into an integrated coherency management structure that operates as a unified hardware subsystem. By combining these functions into a single architectural unit within the memory controller, the patent reduces overall device complexity compared to having separate hardware components, while still achieving hardware-based coherency management that improves operational efficiency.
Solution Approach 2:
The patent designs the snoop filter bank and cache tag bank to serve multiple functions: monitoring cache coherency, tracking memory access patterns, and managing snoop requests. This multi-functionality allows the hardware structure to handle various coherency scenarios without requiring additional specialized components, thereby improving operational efficiency while minimizing the increase in device complexity.
3Reliability
If snoop requests are issued to all devices, then coherency is maintained, but communication overhead increases leading to performance degradation
Solution Approach 1:
The patent implements local quality by making snoop request issuance selective rather than universal. The snoop filter bank analyzes the specific characteristics of each memory access request and determines whether a snoop request is actually needed based on local conditions such as cache state and access patterns. This targeted approach maintains coherency only when necessary, reducing communication overhead and preventing performance degradation from unnecessary snoop requests.
Solution Approach 2:
The patent applies preliminary action by using the snoop filter bank to pre-evaluate memory access requests before issuing snoop requests to other devices. The filter bank proactively determines in advance whether a snoop request is required based on the current cache state and access patterns, allowing the system to avoid unnecessary communication overhead while ensuring coherency is maintained when actually needed.
Data Source
AI summary
A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.