Credit Buffer Cache Region for Processor Data Transmission
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Solution Overview
Problem
Current processor systems with network-on-chip (NOC) technology face inefficiencies in data transmission and caching due to the need for separate caches and external data buffering, leading to increased bandwidth consumption and energy waste.
Innovation Solution
Implementing a credit-based flow control mechanism within a processor's credit buffer, which dynamically allocates a cache region for data caching, allowing for efficient data storage and retrieval by managing write indices and credit grants between source and destination processing devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate caches and external data buffering are used for data transmission, then data storage and retrieval functions are provided, but bandwidth consumption increases and energy is wasted
Solution Approach 1:
The patent combines the cache function and external data buffering function into a single integrated credit buffer structure. The credit buffer simultaneously performs credit-based flow control and data caching, eliminating the need for separate cache modules and external buffers. This merging reduces bandwidth consumption and energy waste while maintaining data storage and retrieval capabilities.
2Reliability
If separate caches and external data buffering are used for data transmission, then data storage and retrieval functions are provided, but bandwidth consumption increases
Solution Approach 1:
The patent merges cache and external buffer functions into the credit buffer, allowing data to be cached and buffered within the same structure. This eliminates redundant data transmission between separate cache and buffer modules, reducing bandwidth consumption while maintaining full data storage and retrieval functionality.
Solution Approach 2:
The credit buffer is designed to perform multiple functions simultaneously: credit-based flow control, data caching, and external data buffering. This multi-functionality eliminates the need for dedicated separate structures for each function, thereby reducing overall bandwidth consumption and resource usage.
3Productivity
If a credit buffer with integrated cache region is used, then bandwidth waste is reduced and data access efficiency is enhanced, but the credit buffer structure becomes more complex
Solution Approach 1:
The credit buffer is segmented into a cache region and a non-cache region, allowing differentiated handling of data. The cache region stores frequently accessed data for fast retrieval, while the non-cache region handles other data operations. This segmentation improves data access efficiency without requiring a completely new complex structure.
Solution Approach 2:
The patent implements dynamic allocation and management of the cache region within the credit buffer. The cache region can be dynamically adjusted based on data access patterns and credit availability, optimizing data access efficiency while managing structural complexity through flexible, adaptive configuration rather than fixed complex architecture.
Data Source
AI summary
Provided is a processor including a plurality of devices. The processor includes a source processing device configured to identify data to request from another device, and a destination processing device configured to, in response to a request for the identified data from the source processing device using credit-based flow control, transmit the identified data to the source processing device using the credit-based flow control. The source processing device includes a credit buffer used for the credit-based flow control, the credit buffer being allocable to include a cache region configured to cache the transmitted identified data received by the source processing device.