Credit-Based Flow Control Circuit Latency Reduction
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Solution Overview
Problem
Existing credit-based flow control solutions for synchronous communications links require large FIFOs and introduce significant latency due to the separate transmission of credits, leading to increased chip area and complexity.
Innovation Solution
A communications link design where credits are generated based on read operations from synchronous FIFOs within the same clock domain, allowing credits to be transmitted using the same clock signal as data, significantly reducing latency and FIFO size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If credits are transmitted separately from data using different clock domains, then flow control reliability is improved, but latency increases and chip area expands
Solution Approach 1:
The patent combines credit transmission with data transmission by using the same clock domain and communication channel. Credits are encoded in the channel busy indicator (CBI) signal that already accompanies data transmissions, eliminating the need for separate credit transmission paths and reducing latency while maintaining flow control reliability
2Reliability
If separate credit transmission paths are used, then flow control accuracy is improved, but device complexity increases
Solution Approach 1:
The patent makes the existing CBI signal serve dual purposes: indicating channel busy status for data transmission and carrying credit information for flow control. This multi-functionality eliminates the need for separate credit transmission circuits while maintaining accurate flow control through the unified credit management logic
3Reliability
If large FIFOs are used to accommodate separate credit transmission, then overflow prevention is improved, but chip area increases
Solution Approach 1:
The patent implements preliminary credit generation within the same clock domain, allowing credits to be prepared and transmitted alongside data rather than requiring large FIFO buffers to store credits pending separate transmission. This reduces the buffering requirement while ensuring overflow prevention through timely credit availability
Data Source
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AI summary
The invention concerns a receiving circuit of a communications link comprising: a first data buffer (336) configured to input, under control of a first clock signal (CLK_V"), data of a first data stream transmitted by a transmitting circuit (302), and to generate a credit trigger signal indicating when a data value is read from the first data buffer (336), wherein data is read from the first data buffer (336), or from a further data buffer (338) coupled to the output of the first data buffer (336), under control of a second clock signal (CLK R); and a credit generation circuit (342) configured to generate, based on the credit trigger signal, a credit signal for transmission to the transmitting circuit (302) under control of the first clock signal (CLK_V"), the credit signal indicating that one or more further data values of the first data stream can be transmitted by the transmitting circuit.