Credit-Based Flow Control for Tile Interconnects
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Solution Overview
Problem
In parallel processing environments, existing technologies face challenges in efficiently managing data flow and buffer storage across tiles in integrated circuits, leading to inefficiencies and increased costs due to the high cost and power consumption of FPGAs compared to ASICs, while maintaining performance and reconfigurability.
Innovation Solution
A method for controlling data flow in integrated circuits with a plurality of tiles, each comprising a processor, a switch for forwarding data, and a receive buffer, where a credit-based flow control technique is used to manage data transmission, allowing data to be sent to a memory when the receive buffer is full, and maintaining a count of outstanding unacknowledged data up to a credit limit, with the credit limit set larger than the buffer size to prevent overflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a receive buffer is used to store data from the switch, then data flow management is improved, but buffer overflow risk increases when data transmission rate exceeds buffer capacity
Solution Approach 1:
The patent implements a credit-based flow control mechanism where the sender maintains a credit counter that is decremented when data is sent and incremented when acknowledgments are received. This feedback loop allows the sender to dynamically adjust its transmission rate based on the receiver's buffer status, preventing buffer overflow while maximizing data throughput. The credit limit is set to the receive buffer size, creating a direct feedback relationship between buffer capacity and transmission control.
2Productivity
If the credit limit is set larger than the receive buffer size, then data transmission throughput is improved, but memory usage for overflow storage increases
Solution Approach 1:
The patent allocates a predetermined overflow buffer of size B=P×N×S bits in memory before data transmission begins, where P is the number of tiles, N is the maximum number of outstanding data units, and S is the data unit size. This preliminary allocation ensures that when the credit limit exceeds the receive buffer size (enabling higher throughput), the overflow data has pre-allocated storage space, preventing unbounded memory usage. The overflow buffer acts as a safety mechanism prepared in advance.
3Adaptability or versatility
If FPGAs are used to maintain reconfigurability, then adaptability is improved, but power consumption and cost increase significantly
Solution Approach 1:
The patent implements dynamic flow control parameters that can be adjusted based on runtime conditions. The credit limit and overflow buffer size are configured based on the specific application requirements, allowing the system to adapt its behavior dynamically. This dynamic configuration capability provides FPGA-like adaptability at the system level without requiring reconfigurable hardware, thereby reducing power consumption and cost while maintaining the ability to optimize performance for different applications.
Data Source
AI summary
The flow of data in an integrated circuit is controlled. The integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a receive buffer to store data from the switch. At a first tile, a count is maintained of data that has been sent to a second tile without receiving an acknowledgement up to a credit limit. At the second tile, data that arrives from the first tile when the receive buffer is full is sent to a memory outside of the tile.