Crest Factor Reduction via Periodic Partial Signals
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Solution Overview
Problem
Existing multi-carrier communication systems, such as DMT, face challenges in reducing the crest factor of signals, particularly in VDSL systems, which results in high maximum amplitudes and increased complexity and costs for processing, due to the large frame length and limited capacity of existing methods.
Innovation Solution
A method and device that generate a correction signal as a combination of partial correction signals with predetermined frequencies, where the frequencies are selected to create a periodic correction signal with a period length shorter than the signal, significantly reducing computational complexity by only requiring the calculation of one period of the correction signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing crest factor reduction methods are used in VDSL systems, then the crest factor can be reduced, but the computational complexity is high and the processing capacity is limited due to large frame lengths
Solution Approach 1:
The correction signal is segmented into multiple partial correction signals, each corresponding to a different frequency component. This segmentation allows the complex correction task to be divided into manageable parts that can be processed independently and then combined, significantly reducing the computational burden while maintaining effective crest factor reduction.
Solution Approach 2:
The patent exploits the periodic nature of the correction signal by identifying and utilizing its repeating pattern. Instead of processing the entire long-frame correction signal, the method identifies the fundamental period and generates the complete correction signal by repeating this shorter period multiple times, dramatically reducing computational complexity.
2Object-generated harmful factors
If the crest factor is reduced using traditional methods, then peak amplitudes are lowered, but the required processing capacity and chip area increase
Solution Approach 1:
By segmenting the correction into partial correction signals at different frequencies, the patent reduces the computational load required to generate and apply the correction, thereby reducing the processing capacity needed and the associated chip area while still achieving effective peak amplitude reduction.
Solution Approach 2:
The periodic structure of the correction signal allows the system to use a shorter computation period that is repeated, reducing the real-time processing requirements and the hardware resources (chip area) needed to implement the crest factor reduction function.
Data Source
AI summary
A method and a device for reducing the crest factor of a signal is operable to generate a correction signal as a combination of a plurality of partial correction signals having respectively predetermined frequencies and a signal having a reduced crest factor being issued as a differential between the correction signal and the signal. The respectively predetermined frequencies are selected such that the correction signal, which has a period length that is shorter than a length of the signal, is periodic. Therefore, according to the invention, only one period of the correction signal is determined and the correction signal is then determined as a periodic continuation of the one period.