Critical-Path Clock Generation Across PVT Variation
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Solution Overview
Problem
Conventional clock generation circuits in semiconductor manufacturing are limited by variability in integrated circuit characteristics across process, voltage, and temperature, leading to suboptimal performance and increased costs due to the need for crystal frequency references.
Innovation Solution
A clock generation circuit that tracks the critical path across process, voltage, and temperature variations using multiple delay chains modeling different delay characteristics, allowing for a variable clock signal that adapts to manufacturing and operating conditions, reducing the need for crystal oscillation sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed maximum clock frequency is specified based on worst-case process, voltage, and temperature variations, then reliability is improved, but productivity deteriorates due to suboptimal performance
Solution Approach 1:
The patent implements dynamic frequency adjustment by using multiple delay chains with different delay characteristics that are selectively activated based on detected operating conditions (voltage and temperature). This allows the clock frequency to dynamically adapt to current PVT conditions rather than being fixed at a conservative worst-case value, thereby resolving the contradiction between reliability and productivity.
Solution Approach 2:
The system changes the clock frequency parameter based on detected operating conditions. By monitoring voltage and temperature and selecting appropriate delay chains, the system adjusts the clock frequency to match actual circuit capabilities under current conditions, enabling higher performance when conditions permit while maintaining reliability when conditions are adverse.
2Reliability
If crystal frequency references are used to provide stable clock signals, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent creates an on-chip copy of the critical path delay characteristics using delay chains that model the timing behavior of the actual circuit. This copy is used to generate a clock signal that naturally tracks the critical path without requiring external crystal references, thereby reducing device complexity and cost while maintaining the reliability needed for synchronous operation.
Solution Approach 2:
The system uses its own critical path characteristics (modeled by on-chip delay chains) to generate the clock signal, rather than relying on external components. The delay chains self-adjust to reflect actual circuit timing under current operating conditions, providing a self-service mechanism that eliminates the need for external crystal references and reduces overall system complexity.
3Adaptability or versatility
If multiple delay chains with different delay characteristics are used to track critical path, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent segments the delay modeling function into multiple specialized delay chains, each designed with specific delay characteristics that match different portions of the critical path under different operating conditions. This segmentation allows the system to cover a wide range of PVT variations by selecting the appropriate segment (delay chain) for current conditions, achieving high adaptability while keeping each individual chain relatively simple.
Data Source
AI summary
Clock generation circuit that track critical path across process, voltage and temperature variation. In accordance with a first embodiment of the present invention, an integrated circuit device includes an oscillator electronic circuit on the integrated circuit device configured to produce an oscillating signal and a receiving electronic circuit configured to use the oscillating signal as a system clock. The oscillating signal tracks a frequency-voltage characteristic of the receiving electronic circuit across process, voltage and temperature variations. The oscillating signal may be independent of any off-chip oscillating reference signal.