Mapping Critical Path Components to High-Level Synthesis Source Code
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Solution Overview
Problem
In programmable integrated circuits, users face challenges in optimizing the critical path of a custom logic circuit due to the inability to map components back to high-level synthesis source code, limiting performance enhancement.
Innovation Solution
The method involves generating a compiler intermediate representation and hardware description from high-level synthesis source code, identifying critical paths in the netlist, and mapping these components back to the source code, allowing designers to modify and optimize the source code for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If critical path analysis is performed on gate-level netlist, then performance limitations can be identified, but the inability to map components back to high-level synthesis source code prevents effective optimization
Solution Approach 1:
The patent introduces an intermediary mapping mechanism that connects gate-level netlist components back to high-level synthesis source code constructs. This mapping system acts as a mediator, allowing designers to trace critical path components through multiple compilation stages (HLS to RTL to netlist) and identify the corresponding source code lines that need modification, thus resolving the disconnect between analysis and optimization
Solution Approach 2:
The patent implements a feedback loop by reporting critical path information back to the high-level synthesis source code level. Instead of leaving designers with only gate-level information, the system provides feedback that includes mappings to original source constructs, enabling designers to make informed modifications at the highest level of abstraction and iteratively optimize performance
2Productivity
If high-level synthesis source code is used for design, then productivity is improved through higher-level abstraction, but the ability to optimize critical path is reduced due to loss of detailed component information
Solution Approach 1:
The patent adds another dimension to the design information by maintaining mappings across multiple abstraction levels (HLS, RTL, netlist) simultaneously. This multi-dimensional information structure allows designers to work at the convenient high-level abstraction while having access to detailed gate-level critical path information when needed, effectively combining the benefits of both levels
3Reliability
If gate-level netlist is analyzed for critical path, then performance bottlenecks can be located, but the complexity of mapping back to source code increases without the proper mapping mechanism
Solution Approach 1:
The patent performs preliminary action by establishing and maintaining component mappings during the compilation process itself, rather than attempting to create mappings after the netlist is generated. The mapping information is preserved through each compilation stage (HLS to RTL to netlist), making the reverse mapping process straightforward and automated rather than complex and manual
Data Source
AI summary
Methods and apparatus for implementing a programmable integrated circuit using circuit design tools are provided. The circuit design tools may receive a high-level synthesis source code, parse the high-level synthesis source code to generate a compiler intermediate representation, process the compiler intermediate representation to generate a register transfer level (RTL) description, and then synthesize and compile the RTL description to generate an output netlist. Timing analysis may be performed on the output netlist to identify a critical path. Components in the critical path may be mapped back to specific portions in the RTL descriptions, to specification portions of the compiler intermediate representation, and to specific lines in the high-level synthesis source code. The designer can then optimize the high-level synthesis source code to shorten the critical path. This process may be iterated as many times as desired.