Critical Path Sensitization Using Existing Scan Chains
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for critical path sensitization in electronic systems, such as integrated circuits, result in increased area and power consumption, design complexity, and performance degradation due to the use of additional logic gates and inefficient scan chain configurations, leading to inaccurate sensitization of both functionally valid and invalid paths.
Innovation Solution
A sensitizing circuit comprising a control circuit and multiple scan chains is used to identify and configure only functionally valid critical paths, utilizing existing scan chains with configuration datasets to maintain predetermined logic levels, thereby avoiding additional gates and reducing run/test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional logic gates are used to sensitize critical paths, then sensitization accuracy is improved, but area and power consumption increase
Solution Approach 1:
The patent extracts and utilizes existing scan chains that are already present in the IC for their original testing purposes, rather than adding new logic gates. By configuring these existing scan chains to maintain predetermined logic levels, the patent achieves critical path sensitization without requiring additional gates, thereby avoiding the area penalty while maintaining sensitization accuracy.
Solution Approach 2:
The patent makes the existing scan chains serve dual purposes: their original testing function and the additional function of critical path sensitization. By configuring scan chains to maintain predetermined logic levels on non-critical inputs, the patent enables sensitization without adding dedicated sensitization hardware, thus achieving multi-functionality and avoiding area increase.
2Measurement precision
If additional logic gates are used to sensitize critical paths, then sensitization accuracy is improved, but power consumption increases
Solution Approach 1:
The patent extracts and utilizes existing scan chains that are already present in the IC for their original testing purposes, rather than adding new logic gates. By configuring these existing scan chains to maintain predetermined logic levels, the patent achieves critical path sensitization without requiring additional gates, thereby avoiding the power consumption penalty while maintaining sensitization accuracy.
Solution Approach 2:
The patent makes the existing scan chains serve dual purposes: their original testing function and the additional function of critical path sensitization. By configuring scan chains to maintain predetermined logic levels on non-critical inputs, the patent enables sensitization without adding dedicated sensitization hardware, thus achieving multi-functionality and avoiding additional power consumption.
3Reliability
If all scan chains are concatenated to configure scan flip-flops, then sensitization coverage is improved, but run time and test time increase significantly
Solution Approach 1:
The patent segments the scan chains and selectively configures only those scan chains that are associated with critical path elements. Instead of concatenating all scan chains into a single long chain, the patent identifies and configures specific scan chains that contain scan flip-flops coupled to critical path elements, thereby reducing the total configuration time while maintaining complete sensitization coverage of all critical paths.
Solution Approach 2:
The patent performs preliminary identification of which scan chains are associated with critical path elements before configuration. By pre-determining the relevant scan chains and their required configurations, the patent avoids the time-consuming process of configuring all scan chains, thereby reducing test time while ensuring complete sensitization coverage through targeted configuration of only the necessary scan chains.
4Measurement precision
If additional gates are placed in functional paths, then critical path sensitization is achieved, but design complexity and timing requirements worsen
Solution Approach 1:
The patent extracts and utilizes existing scan chains that are already present in the IC for their original testing purposes, rather than adding new logic gates. By configuring these existing scan chains to maintain predetermined logic levels, the patent achieves critical path sensitization without requiring additional gates, thereby avoiding increased design complexity while maintaining sensitization capability.
Solution Approach 2:
The patent makes the existing scan chains serve dual purposes: their original testing function and the additional function of critical path sensitization. By configuring scan chains to maintain predetermined logic levels on non-critical inputs, the patent enables sensitization without adding dedicated sensitization hardware, thus achieving multi-functionality and avoiding increased design complexity.
5Measurement precision
If additional gates are placed in functional paths, then critical path sensitization is achieved, but timing requirements worsen
Solution Approach 1:
The patent extracts and utilizes existing scan chains that are already present in the IC for their original testing purposes, rather than adding new logic gates. By configuring these existing scan chains to maintain predetermined logic levels, the patent achieves critical path sensitization without requiring additional gates, thereby avoiding additional propagation delays and maintaining original timing requirements.
Solution Approach 2:
The patent makes the existing scan chains serve dual purposes: their original testing function and the additional function of critical path sensitization. By configuring scan chains to maintain predetermined logic levels on non-critical inputs, the patent enables sensitization without adding dedicated sensitization hardware, thus avoiding additional gates that would introduce propagation delays and worsen timing requirements.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An electronic system, comprising a critical logic circuit, various scan chains, and a control circuit, is provided. The critical logic circuit includes a critical path. One or more scan chains of the electronic system are coupled to the critical logic circuit and are associated with sensitization of the critical path. The control circuit may receive one or more configuration datasets, where each configuration dataset includes a scan chain identifier and a test pattern. For each received configuration dataset, the control circuit may identify a scan chain, of the one or more scan chains, that is associated with the scan chain identifier, and load the identified scan chain with the test pattern. Some scan flip-flops of the loaded one or more scan chains are utilized to sensitize the critical path.