Configurable Critical Path Emulation for Adaptive Voltage Scaling
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Solution Overview
Problem
Existing voltage scaling architectures for system-on-chip platforms face challenges in efficiently managing power consumption due to variations in IC chips caused by fabrication processes, voltage supply, and temperature conditions, leading to suboptimal operating voltages and increased power usage.
Innovation Solution
A configurable delay circuit with a lookup table and sampling circuit is used to emulate critical paths in data processors, allowing for adaptive voltage scaling by monitoring delays and adjusting the power supply voltage to minimize power consumption while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed operating voltage is used for all IC chips, then all chips can operate reliably, but power consumption increases due to suboptimal voltage levels for individual chip variations
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the operating voltage based on measured critical path delays. The system changes the voltage parameter from a fixed value to a variable value optimized for each chip's actual performance characteristics, thereby reducing power consumption while maintaining reliability.
Solution Approach 2:
The patent implements feedback through a closed-loop system that measures critical path delays using delay elements and sampling circuits, compares measurements against thresholds, and adjusts operating voltage accordingly. This feedback mechanism enables the system to adapt to individual chip variations and optimize power consumption while ensuring operational reliability.
2Use of energy by moving object
If voltage is reduced to save power, then power consumption decreases, but timing violations occur due to increased delay variability
Solution Approach 1:
The feedback mechanism continuously monitors critical path delays and adjusts voltage to maintain timing reliability. By measuring actual delay values and comparing them against thresholds, the system determines the maximum voltage reduction that does not cause timing violations, thereby optimizing power consumption while preserving timing reliability.
Solution Approach 2:
The system performs preliminary characterization of critical path delays during manufacturing or initialization, storing delay measurements and thresholds for later use. This preliminary action enables the system to quickly determine safe operating voltage levels without causing timing violations, facilitating power optimization from the start of operation.
3Use of energy by moving object
If individual chip characterization is performed, then optimal voltage levels can be determined, but characterization time and complexity increase
Solution Approach 1:
The patent performs chip characterization during manufacturing or initialization, storing critical path delay measurements and optimal voltage levels in lookup tables or configuration memory. This preliminary characterization eliminates the need for time-consuming measurements during operation, enabling quick voltage optimization while minimizing characterization time impact on production and deployment.
Solution Approach 2:
The system creates a simplified model or representation of each chip's critical path characteristics through delay measurements, storing this information in lookup tables. This copying approach captures essential chip variations without requiring complex continuous characterization, enabling fast voltage optimization based on pre-stored data.
4Measurement precision
If more delay elements are added to accurately model critical paths, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent segments the critical path into multiple discrete delay elements, each representing a portion of the overall critical path. This segmentation allows accurate measurement of total delay through combination of individual element measurements while keeping each element simple and manageable, balancing measurement precision with device complexity.
Data Source
AI summary
The subject matter of this application is embodied in an apparatus that includes a configurable delay circuit comprising a plurality of delay elements, and a lookup table having information for configuring the delay circuit based on one or more conditions. The apparatus also includes a controller to configure the delay circuit according to the information in the lookup table, and a sampling circuit to sample outputs of each of a subset of the delay elements and generate a multi-bit delay signal providing information about an amount of delay caused by the delay elements to an input signal propagating through the configurable delay circuit. Each bit in the multi-bit delay signal indicates whether the input signal has propagated through a corresponding delay element.