Criticality-Based Evaluation for Fault-Tolerant Processing Assemblies

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Solution Overview

Problem

Dedicated hardware accelerators for computationally intensive tasks, such as neural networks, are prone to hardware failures due to manufacturing variations and aging, leading to temporary and permanent errors, which can compromise their functionality, especially in safety-critical applications.

Innovation Solution

A method for fault-tolerant mapping by assigning criticality information to each structure within a processing assembly, allowing for modified or omitted evaluation of structures based on their criticality, ensuring minimal mapping errors even with malfunctioning processing units, thereby maintaining system functionality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the integrated circuitry is made with the smallest structure sizes to reduce power consumption and cost, then power consumption and cost are reduced, but the hardware becomes more prone to failures

Engineering Contradiction:
Improvepower consumptionVSAvoidhardware failure rate
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The system performs preliminary actions by assigning criticality information to each structure before processing begins. When a processing unit malfunctions, the system has already prepared the information needed to identify which structures are critical and which can be skipped, allowing rapid adaptation without redundant hardware.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the parameter of structure evaluation by using criticality information to determine whether to evaluate a structure fully, partially, or skip it entirely. This dynamic parameter adjustment allows the system to maintain functionality with reduced hardware resources when failures occur.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If redundant design is implemented to maintain system functionality during failures, then reliability is improved, but device complexity and cost increase

Engineering Contradiction:
Improvesystem functionality during failuresVSAvoidredundant design structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of implementing full redundancy, the system applies partial action by selectively evaluating only the most critical structures when failures occur. The criticality information enables the system to focus computational resources on essential structures, achieving fault tolerance without duplicating the entire processing assembly.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The system discards non-critical structures when failures occur, using the pre-assigned criticality information to identify which structures can be safely skipped. This allows the system to recover functionality by focusing on essential structures rather than maintaining redundant copies of all structures.

Inventive Principle:
Principle #34Discarding and recovering

3Measurement precision

If all structures are evaluated to ensure accurate mapping output, then mapping precision is improved, but processing time increases when processing units malfunction

Engineering Contradiction:
Improvemapping accuracyVSAvoidprocessing time during failures
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The system performs preliminary action by pre-assigning criticality information to each structure before processing begins. This allows the system to quickly determine which structures require evaluation and which can be skipped, avoiding time-consuming decisions during actual processing when failures occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system applies local quality by evaluating structures with different levels of scrutiny based on their criticality. Critical structures receive full evaluation to maintain mapping accuracy, while non-critical structures are skipped or partially evaluated, reducing overall processing time during failures.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250335322A1Method for Fault Tolerant Implementation of a Mapping of at Least One Input Value to at Least One Output Value by a Processing Assembly having a Plurality of Processing Units and a Processing Assembly
Publication Date: 2025.10.30 ROBERT BOSCH GMBH
  • US20250335322A1 patent drawing
  • US20250335322A1 patent drawing

AI summary

A method for fault tolerant implementation of a mapping of at least one input value to at least one output value by a processing assembly with a plurality of processing units is disclosed. The mapping includes a plurality of structures with computational operations which can be evaluated by one or more of the processing units. Each of the structures is associated with criticality information that includes information how critical the error-free evaluation of the structure is for the error-free evaluation of the mapping. If at least one processing unit has a malfunction, at least one structure is selected based on the criticality information of the structures. It is determined whether the at least one structure should be evaluated in a modified manner or not evaluated. The mapping is applied to input values, wherein the selected at least one structure is evaluated in a modified manner or is not evaluated.