Cross-Shaped Active Region Transistors for Memory Area Reduction
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Solution Overview
Problem
The increasing number of memory cells in semiconductor devices leads to a larger area requirement due to the increased number of high voltage transistors needed for program and pass voltages, which complicates the design and integration of memory blocks.
Innovation Solution
The semiconductor device incorporates a switch unit with multiple pass transistors sharing a single junction area, arranged in a cross-shaped active region on the semiconductor substrate, to efficiently transmit operation voltages to word lines across multiple memory blocks, thereby reducing the overall area occupied by the switch unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to implement high capacity, then the storage capacity is improved, but the area occupied by high voltage transistors increases
Solution Approach 1:
Multiple pass transistors (first to fourth pass transistors) share a common active region, merging what would traditionally be separate transistor structures into a unified configuration. This allows four transistors to function with one shared active region rather than requiring four separate active regions, directly reducing the area occupied by high voltage transistors while supporting increased memory cell capacity
Solution Approach 2:
The shared active region serves multiple functions by being controlled by different gate electrodes (first to fourth gate electrodes) to enable multiple pass transistors to operate independently. This multi-functional design allows a single active region structure to replace what would traditionally require multiple separate active regions, reducing overall area while maintaining the ability to transmit high voltages to multiple word line groups
2Adaptability or versatility
If the number of high voltage transistors is increased to transmit operation voltage to more word lines, then the voltage transmission capability is improved, but the device area increases
Solution Approach 1:
The patent merges multiple transistor functions into a single shared active region structure. The first to fourth pass transistors all share the same active region, which is controlled by respective gate electrodes. This merging approach maintains the ability to transmit operation voltages to multiple word line groups while using only one active region instead of four separate ones, thereby reducing device area
Solution Approach 2:
The patent transitions from a planar arrangement where each transistor would occupy separate two-dimensional space to a configuration where multiple transistors are stacked or arranged around a shared active region. This dimensional reorganization allows multiple voltage transmission paths to coexist in a more compact three-dimensional arrangement, improving voltage transmission capability without proportionally increasing device area
Data Source
AI summary
Disclosed is a semiconductor device, including: an active region defined in a shape extended in at least four different directions in a semiconductor substrate; and gates of first to fourth transistors formed on extended portions of the active region, respectively, in which the first to fourth transistors share one junction area.