Cross-Bus Memory Mapping for Zero-Copy PCIe Data Transfer
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Solution Overview
Problem
Current networked hardware storage devices face challenges in reducing storage staging buffer copies and improving IO operations per second (TOPS) while maintaining low latency, particularly in scenarios involving multiple operating systems and PCIe bus interactions.
Innovation Solution
The implementation of cross-bus memory mapping using a memory key to facilitate direct data access between different PCIe buses, enabling zero-copy data transmission and reducing the need for CPU involvement, through the use of a subsystem that maps memory from one bus to another, and employing NVMe emulation software to handle operations across operating systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional storage staging buffer copies are used for data transmission between PCIe buses, then data can be transferred between different operating systems, but the number of buffer copies increases and CPU utilization increases, reducing IO operations per second and increasing latency
Solution Approach 1:
The patent introduces a cross-PCIe memory mapping mechanism that acts as an intermediary between different PCIe buses and operating systems. Instead of copying data through multiple buffers, the memory mapping mechanism enables direct access to remote memory buffers across PCIe boundaries, eliminating intermediate copying stages while maintaining system abstraction and compatibility
Solution Approach 2:
The patent extracts the data copying operation from the traditional storage staging buffer path by implementing zero-copy RDMA operations. The memory buffer is directly mapped across PCIe buses, removing the intermediary buffer copying step entirely and allowing data to flow directly from source to destination without being taken out and reinserted into intermediate buffers
2Loss of time
If traditional storage staging buffer copies are used for data transmission, then data can be transferred between PCIe buses, but latency increases due to multiple buffer copies and CPU involvement
Solution Approach 1:
The patent implements self-service data transfer by enabling direct memory-to-memory operations between PCIe domains without CPU intervention. The RDMA engine autonomously handles the data transmission using the cross-PCIe memory mapping, eliminating the need for CPU to service each buffer copy operation, thereby reducing latency and improving transfer efficiency simultaneously
3Ease of operation
If cross-bus memory mapping is implemented, then zero-copy data transmission is achieved and CPU involvement is reduced, but system complexity increases due to memory mapping mechanisms
Solution Approach 1:
The patent implements a universal cross-PCIe memory mapping mechanism that can be applied to any PCIe bus configuration and operating system combination. The memory mapping system provides multi-functional support for different data transfer scenarios, protocols, and memory types through a unified interface, making the complex operation transparent and easy to use across diverse system configurations
Data Source
AI summary
A computerized system for efficient interaction between a host, the host having a first operating system, and a second operating system, the system comprising a subsystem on the second operating system which extracts data, directly from a buffer which is local to the host, wherein the system is operative for mapping memory from one bus associated with the first operating system to a different bus, associated with the second operating system and from which different bus the memory is accessed, thereby to emulate a connection between the first and second operating systems by cross-bus memory mapping.