Semiconductor package
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Solution Overview
Problem
Semiconductor packages with multiple chips are prone to warpage due to differences in coefficients of thermal expansion, leading to structural bending and complications in manufacturing, particularly after the formation of the second molding layer.
Innovation Solution
The arrangement of upper semiconductor chips intersecting the direction of lower chips on a redistribution structure, overlapping vulnerable regions, provides additional rigidity to alleviate warpage by reinforcing structures susceptible to thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are mounted on a single interposer or package substrate, then high functionality and miniaturization are achieved, but warpage phenomenon occurs due to differences in coefficients of thermal expansion
Solution Approach 1:
The package structure is divided into multiple layers including lower semiconductor chips, an interposer substrate, and upper semiconductor chips. This segmentation allows each layer to be optimized independently for thermal expansion characteristics, reducing overall warpage while maintaining high functionality through multi-chip integration.
Solution Approach 2:
The patent employs composite material structures including the interposer substrate made of materials with intermediate thermal expansion coefficients between silicon chips and organic substrates. This composite approach creates a gradient structure that compensates for thermal mismatch, preventing warpage while enabling high-density chip integration.
2Volume of moving object
If multiple semiconductor chips are mounted on a single interposer or package substrate, then miniaturization is achieved, but warpage phenomenon occurs due to differences in coefficients of thermal expansion
Solution Approach 1:
The compact package is segmented into multiple functional layers (lower chips, interposer, upper chips) that can be stacked vertically. This segmentation enables miniaturization by utilizing the third dimension while the layered structure inherently manages thermal stress distribution, preventing warpage in the compact form factor.
Solution Approach 2:
The patent transitions from planar chip arrangement to three-dimensional stacking with lower and upper chips connected through the interposer substrate. This dimensional change achieves miniaturization by reducing footprint area while the vertical layering provides thermal expansion management, preventing warpage in the compact structure.
3Adaptability or versatility
If semiconductor packages employ a plurality of semiconductor chips, then high functionality is achieved, but severe warpage occurs due to differences in coefficients of thermal expansion
Solution Approach 1:
The interposer substrate acts as a composite material bridge between dissimilar chip materials, providing mechanical strength and thermal expansion compatibility. This composite structure maintains structural integrity under thermal cycling while supporting multiple functional chips, enabling high functionality without severe warpage.
Solution Approach 2:
The interposer substrate serves as an intermediary layer between lower and upper semiconductor chips, mediating the thermal expansion differences. This intermediary structure distributes thermal stresses uniformly, maintaining structural integrity while enabling the integration of multiple functional chips with different material properties.
Data Source
AI summary
A semiconductor package includes a redistribution substrate having a first surface including first and a second regions and a second surface opposite to the first surface, and including a first redistribution layer, first and second semiconductor chips positioned in a first direction on the first region the redistribution substrate, each of the first and second semiconductor chips being electrically connected to the first redistribution layer, a first molding layer on the first region on the first and second semiconductor chips, a redistribution structure on the first molding layer and including a second redistribution layer, conductive posts on the first region and electrically connecting the first redistribution layer to the second redistribution layer, third and fourth semiconductor chips positioned in a second direction, intersecting the first direction, and each electrically connected to the second redistribution layer, and a second molding layer on the second region the redistribution substrate and on the third and fourth semiconductor chips.