Cross-Chip Passive Component Structure for IC Surface Area Limits
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Solution Overview
Problem
The increasing complexity of integrated circuits (ICs) has led to surface area constraints, limiting the implementation of desired features, as existing methods for connecting multiple IC chips do not effectively utilize passive components across multiple chips, resulting in inefficient use of space.
Innovation Solution
A method and system that fabricate passive components by generating a three-dimensional model with a first portion in one chip, including all ports and simulating electrical operation, and a second portion in another chip, without ports, allowing the passive component to traverse the interface between the chips, enabling efficient use of space and functionality across multiple semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If passive components are formed entirely within a single IC chip, then the component structure is simple and easy to manufacture, but the surface area occupied is large, limiting the implementation of additional features
Solution Approach 1:
The passive component is divided into two segments: a first portion formed in a first IC chip and a second portion formed in a second IC chip. This segmentation allows the component to span multiple chips, reducing the surface area requirement on any single chip while maintaining the complete functionality of the passive component through the interface between chips.
2Area of stationary object
If multiple IC chips are connected to form a single device, then the surface area per chip is reduced, but the effectiveness is limited because passive components still occupy large areas within individual chips
Solution Approach 1:
The passive component extends into the vertical dimension by traversing the interface between stacked IC chips. This three-dimensional configuration allows the component to utilize space across multiple chips rather than being constrained to a two-dimensional layout on a single chip surface, thereby reducing the surface area footprint while improving overall device effectiveness.
3Adaptability or versatility
If the surface area of IC chips is reduced to accommodate more features, then more features can be implemented, but passive components become even more constrained in space
Solution Approach 1:
By segmenting the passive component across multiple IC chips, the invention enables reduced surface area per chip while maintaining complete passive component functionality. This approach allows more features to be packed into each chip without compromising the performance or size requirements of passive components.
Data Source
AI summary
Embodiments of the disclosure provide a structure including a passive component traversing multiple semiconductor chips, with related systems and methods. A structure of the disclosure includes a plurality of stacked semiconductor chips including a first chip coupled to a second chip through an interface. A passive component traverses the interface between the first chip and the second chip of the plurality of stacked semiconductor chips. The passive component includes a first portion within the first chip and a second portion within the second chip.