Cross-Clock Event Timeline Rendering for SoC Debugging
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Solution Overview
Problem
Debugging complex system-on-chip (SoC) applications is complicated by the separate clock domains of its subsystems, making it difficult to evaluate the relative timing of events across different subsystems.
Innovation Solution
A method and system that sample a system timer in a first clock domain and request subsystem timestamps from timers in different clock domains, translating these timestamps to a system-level timeline using a host processor, thereby synchronizing events across clock domains without interrupting the application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If subsystems operate in separate clock domains to maximize performance, then processing capability is improved, but timing evaluation across subsystems becomes difficult
Solution Approach 1:
The patent introduces a host processor as an intermediary that collects timestamps from multiple subsystem timers operating in different clock domains and translates them to a common system timer reference. This mediator enables timing evaluation across subsystems without requiring them to share the same clock domain, thus preserving processing capability while solving the timing measurement problem.
Solution Approach 2:
The patent changes the reference parameter for timing from subsystem-specific clock domains to a unified system timer reference. By translating timestamps from different clock domains to the system timer's time base, the patent enables consistent timing evaluation across all subsystems while they continue to operate independently in their own clock domains.
2Measurement precision
If traditional synchronization methods are used across clock domains, then timing alignment is achieved, but message traffic and synchronization overhead increase
Solution Approach 1:
The patent performs preliminary sampling of the system timer and subsystem timers to establish offset values before actual event tracing begins. This preliminary synchronization action captures the relative timing relationships between different clock domains, allowing subsequent timestamp translations to be performed efficiently without continuous heavy synchronization overhead during runtime.
Solution Approach 2:
The patent creates a virtual copy of the subsystem timestamps by translating them to the system timer's time reference. Instead of physically synchronizing all subsystems to a common clock domain (which would generate excessive message traffic), the patent copies the timing information and transforms it mathematically to appear as if all events occurred in the same time reference frame.
Data Source
AI summary
Disclosed approaches for rendering event data from subsystems in different clock domains according to a system-level timeline include, for each of multiple subsystems, sampling a system timer in a first clock domain for a first timestamp by a host processor. A host processor requests a subsystem timestamp from a subsystem timer in each of the subsystems. The subsystem timestamp is associated with the first timestamp, and the subsystem timer operates in a clock domain different from the first clock domain. The host processor translates timestamps in traced event data of the subsystems to a timeline of the system timer using the first timestamp and associated subsystem timestamps.