Cross-Connected SiC Trench MOSFET Structure for Lower On-Resistance
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Solution Overview
Problem
The existing SiC MOSFET devices with trench gate structures face a contradiction between channel region resistance and junction field effect transistor (JFET) region resistance, leading to increased total on-resistance and reduced device performance.
Innovation Solution
A semiconductor device with a trench structure design where first trenches extend in one direction and a second trench extends in a perpendicular direction, connecting the first trenches, allowing for a tighter arrangement and higher channel density, reducing on-resistance, and incorporating a second P-type semiconductor region to shield the gate dielectric layer from high electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the spacing between trench gate structures is reduced to decrease cell size and increase channel density, then channel region resistance is reduced, but JFET region resistance increases
Solution Approach 1:
The patent transitions from a conventional planar trench gate structure to a three-dimensional stacked trench gate structure. Multiple trench gates are arranged vertically in different layers, allowing the device to utilize the vertical dimension for increasing channel density without further compressing the horizontal spacing between trenches. This dimensional transition resolves the contradiction by enabling higher channel density while preserving adequate JFET region dimensions for acceptable resistance characteristics.
Solution Approach 2:
The patent divides the gate structure into multiple independent trench gates arranged in stacked layers. Each trench gate operates as a separate conducting channel, and the segmented structure allows independent optimization of each layer's dimensions. This segmentation enables the device to achieve high overall channel density through vertical stacking while maintaining appropriate spacing and dimensions in each individual layer to control JFET region resistance.
2Manufacturing precision
If trench gate structures are tightly arranged to reduce cell size, then channel density increases and channel region resistance decreases, but total on-resistance increases due to increased JFET region resistance
Solution Approach 1:
The patent resolves the total on-resistance issue by moving the density increase strategy to the vertical dimension through stacked trench gates. This allows horizontal trench spacing to be maintained at optimal values for minimizing JFET region resistance, while channel density is increased through vertical stacking. The result is a structure that achieves high channel density without the penalty of excessive JFET region resistance, thereby reducing total on-resistance and energy loss.
Solution Approach 2:
The patent changes the structural parameters from a two-dimensional planar arrangement to a three-dimensional stacked arrangement. This parameter change fundamentally alters how channel density is achieved - not by compressing horizontal spacing (which increases JFET resistance), but by adding vertical layers. This parameter transformation enables simultaneous optimization of both channel density and JFET region characteristics, reducing total on-resistance.
Data Source
AI summary
A semiconductor device includes an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source, and a drain. The trench structure is disposed at the epitaxial layer. The trench structure includes a plurality of first trenches and one second trench. The plurality of first trenches extend in a first direction and are arranged at intervals in a second direction. The second trench extends in the second direction. The second trench and each of the plurality of first trenches are disposed in a cross manner and communicate with each other. The interlayer dielectric layer covers the gate, and has a contact hole that extends in the second direction. The source is disposed at the interlayer dielectric layer, and is in contact, through the contact hole, with the epitaxial layer.