Cross-Connects in Double-Patterned Metal Layers Using Forbidden Zones
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Solution Overview
Problem
Forming crossovers between adjacent parallel route tracks in integrated circuits with desired lateral dimensions is problematic, especially at technology nodes beyond 28 nanometers using 193 nanometer illumination sources, which requires multiple pattern steps and complicates the tradeoff between fabrication costs and yield.
Innovation Solution
A process involving the formation of first and second interconnect patterns in alternating parallel route tracks, with a crossover pattern extending between them, and an exclusion zone free of metal interconnects, using photolithography with dipole or isotropic illumination sources to create continuous metal crossover lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If 193 nanometer illumination sources are used for technology nodes at and beyond 28 nanometers, then fabrication costs can be controlled, but manufacturing precision deteriorates making it difficult to obtain desired first metal interconnect layouts
Solution Approach 1:
The patent divides the metal interconnect formation process into multiple pattern steps. The first metal interconnect layout is formed through sequential patterning operations, where different portions of the interconnect structure are created in separate lithography steps using the 193nm illumination source. This segmentation allows each step to achieve the required precision while maintaining cost control through the use of existing wavelength technology.
Solution Approach 2:
The patent performs preliminary patterning actions to prepare the substrate for subsequent metal deposition. By pre-forming mandrel structures, sacrificial layers, and alignment features before the actual metal interconnect formation, the process ensures that the final metal layout achieves desired precision even when using 193nm illumination, which has limitations at 28nm and below node sizes.
2Manufacturing precision
If multiple pattern steps are used to form first metal interconnect layouts at 28 nanometer node and beyond, then manufacturing precision can be maintained, but device complexity increases
Solution Approach 1:
The patent merges multiple patterning operations into an integrated process flow that shares common process steps, tools, and materials. By combining mandrel formation, spacer deposition, and metal filling into a unified multi-step process using the same 193nm lithography platform, the patent reduces device complexity compared to using entirely different patterning technologies, while still achieving the required manufacturing precision for 28nm and below nodes.
3Manufacturing precision
If crossovers are formed between adjacent parallel route tracks with desired lateral dimensions, then manufacturing precision is maintained, but fabrication yield deteriorates
Solution Approach 1:
The patent introduces intermediary structures such as sacrificial mandrels and spacer layers that mediate the formation of crossover regions. These intermediary elements enable precise control of crossover lateral dimensions through self-aligned processes, reducing variability and improving fabrication yield. The intermediary structures act as templates that guide metal deposition, ensuring consistent crossover geometry without requiring direct patterning of the metal at the crossover location.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process effectively forms continuous metal crossover lines between interconnect patterns while maintaining an exclusion zone free of metal, addressing the challenges of achieving desired dimensions and cost-yield tradeoffs in advanced technology nodes.
Implementation Method 1
forming a first interconnect pattern of interconnect leads in a first plurality of parallel route tracks, and forming a second interconnect pattern of interconnect leads
Data Source
AI summary
An integrated circuit is formed by forming a first interconnect pattern in parallel route tracks, and forming a second interconnect pattern in alternating parallel route tracks. The first interconnect pattern includes a first lead pattern in the parallel route tracks, and the second interconnect pattern includes a second lead pattern in an immediately adjacent route track. The first interconnect pattern includes a crossover pattern which extends from the first lead pattern to the second lead pattern. An exclusion zone in the route track immediately adjacent to the crossover pattern is free of a lead pattern for a lateral distance of two to three times the width of the crossover pattern. Metal interconnect lines are form in the first interconnect pattern and the second interconnect pattern areas, including a continuous metal crossover line through the crossover pattern area. The exclusion zone is free of the metal interconnect lines.