Cross-Core Breakpoint Synchronization in Multi-Core Microcontrollers
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Solution Overview
Problem
In multi-core processor systems with asymmetrical cores, debugging across different processor cores is challenging due to differing memory, peripheral sets, and execution speeds, making it difficult to correlate and synchronize breakpoint events across cores.
Innovation Solution
A method and integrated circuit device that enables communicating processor breakpoints between cores, using cross breakpoint logic and registers to synchronize breakpoints and interrupts across processor cores, even when they operate on different system clocks, allowing for simultaneous or quasi-simultaneous debugging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If breakpoints are implemented in asymmetrical multi-core processors with different memory, peripheral sets, and execution speeds, then debugging capability is improved, but synchronization difficulty increases
Solution Approach 1:
The breakpoint register is designed to serve multiple cores simultaneously with a unified breakpoint address space. The same breakpoint register can trigger breakpoints in different cores based on their execution context, allowing a single debugging mechanism to handle multiple asymmetrical cores without requiring separate breakpoint systems for each core.
Solution Approach 2:
The debug module acts as an intermediary between the breakpoint trigger and the multiple processor cores. When a breakpoint is triggered, the debug module determines which core(s) should be halted based on the current execution context, managing the complexity of synchronization centrally rather than requiring direct coordination between each core pair.
2Reliability
If cross-core breakpoint communication is enabled, then simultaneous debugging across cores is improved, but interrupt controller complexity increases
Solution Approach 1:
The breakpoint interrupt functionality is merged with the existing interrupt controller structure. The breakpoint register can generate interrupts that are routed through the same interrupt controller used for other processor events, consolidating interrupt handling logic and avoiding the need for a separate interrupt management system for breakpoints.
Solution Approach 2:
The interrupt controller is designed to handle multiple types of interrupts including breakpoint interrupts from any core. A single interrupt controller manages interrupts for both master and slave cores, as well as handling the cross-core breakpoint communication, reducing overall system complexity despite the added debugging capability.
3Measurement precision
If breakpoints are synchronized across cores operating on different system clocks, then debugging accuracy is improved, but timing synchronization difficulty increases
Solution Approach 1:
The breakpoint synchronization system uses self-service mechanisms where each core monitors its own execution state and independently determines when to halt based on the breakpoint condition. The debug module coordinates the halting decision, but each core autonomously manages its own clock domain and execution timing, eliminating the need for complex inter-core clock synchronization.
Solution Approach 2:
The debug module serves as a mediator that translates breakpoint conditions into core-specific halt commands. It handles the timing and coordination of breakpoint execution across different clock domains by managing the interrupt generation and core state transitions, isolating the complexity of inter-clock synchronization from the individual cores.
Data Source
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Figure 2
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AI summary
In a debugging method for an integrated circuit device which has multiple processing cores, a debugging breakpoint is activated at a first processor core in the integrated circuit device. Upon activation, the debugging breakpoint stops execution of instructions in the first processor core and the debugging breakpoint is communicated to a second processor core in the integrated circuit device.