Cross-Coupled Cascode Comparator for Low-Noise ADC Decisions
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Solution Overview
Problem
High-resolution analog-to-digital converters require low-power, low-noise comparators to improve signal-to-noise ratio, but existing latched comparators struggle to achieve this balance while maintaining low power consumption.
Innovation Solution
A latched comparator design featuring a pre-amplifier stage with cascode pairs and gain-boosting transistors, which increases gain and makes it time-invariant, allowing for a more controlled decision point with reduced noise, implemented using NMOS transistors and controlled by a clock signal to minimize power consumption and hysteresis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a latched comparator with dynamic pre-amplifier stage is used, then power consumption is reduced, but input-referred noise increases
Solution Approach 1:
The comparator is divided into two distinct stages: a dynamic pre-amplifier stage for initial signal amplification and a latch stage for decision-making. This segmentation allows each stage to be optimized independently - the pre-amplifier operates dynamically at low power while the latch provides stable, low-noise decision output.
Solution Approach 2:
The dynamic pre-amplifier performs preliminary amplification of the differential input signal before it reaches the latch stage. By pre-conditioning the signal with higher gain earlier in the process, the subsequent latch operates with better signal margins, reducing its contribution to input-referred noise while maintaining low power consumption.
2Measurement precision
If the resolution of the ADC is increased, then measurement precision improves, but the noise range of the comparator must be reduced
Solution Approach 1:
The amplification function is segmented into the dynamic pre-amplifier stage, which provides the bulk of the gain needed for high-resolution conversion. This allows the latch stage to operate with reduced sensitivity to noise, enabling high ADC resolution without proportionally increasing the comparator's noise range.
Solution Approach 2:
The pre-amplifier gain is made time-variant through dynamic operation, allowing the gain parameter to be optimized for different phases of operation. During the comparison phase, high gain reduces the effective noise range, enabling high-resolution measurement while maintaining low power consumption.
3Object-affected harmful factors
If the pre-amplifier gain is increased to reduce noise contribution, then input-referred noise decreases, but circuit complexity increases
Solution Approach 1:
The high-gain amplification function is segmented into the dynamic pre-amplifier stage rather than requiring the latch stage to provide all necessary gain. This segmentation allows the use of a relatively simple latch circuit while achieving the required total gain through the pre-amplifier, thus reducing overall circuit complexity compared to using a single high-gain latch.
Solution Approach 2:
The pre-amplifier performs preliminary high-gain amplification before the signal reaches the latch. This preliminary action reduces the noise contribution of subsequent stages and allows the use of a simpler, lower-complexity latch circuit while still achieving the required performance for high-resolution ADC operation.
Data Source
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AI summary
A latched comparator (2) comprises a pre-amplifier stage (4) with a positive input (Vin,p),a negative input (Vin,n); and a differential output (ΔVout) comprising a first output (Vout,1) and a second output (Vout,2), the pre-amplifier stage (4) comprising a first cascode pair (8), comprising a first amplifying transistor (MN2) and a first cascode transistor (MN4) connected at a first cascode node (20), the first amplifying transistor (MN2) being controlled by the positive input (Vin,p) and the first cascode transistor (MN4) being connected, opposite to the first cascode node (20), to the first output (Vout,1); a second cascode pair (10), comprising a second amplifying transistor (MN3) and a second cascode transistor (MN5) connected at a second cascode node (22), the second amplifying transistor (MN3) being controlled by the negative input (Vin,n) and the second cascode transistor (MN5) being connected, opposite to the second cascode node (22), to the second output (Vout,2); a first gain-boosting transistor (MN6) connected between the first output (Vout,1) and the first cascode node (20); and a second gain-boosting transistor (MN7) connected between the second output (Vout,2) and the second cascode node (22), wherein the first gain-boosting transistor (MN6) and the second gain-boosting transistor (MN7) are cross-coupled, so that the first gain-boosting transistor (MN6) is controlled by the second output (Vout,2) and the second gain-boosting transistor (MN7) is controlled by the first output (Vout,2).