Cross-Coupled Cascode TIA Circuit Without Inductive Peaking
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Solution Overview
Problem
High-speed data communication requires high performance trans impedance amplifier (TIA) circuits that achieve optimal gain/bandwidth performance in CMOS receivers for chip-to-chip optical interconnects, but existing solutions often rely on inductive peaking, larger input devices, or additional gain stages, which can reduce bandwidth and increase power consumption, especially as CMOS technology scales into nanometer gate lengths, leading to reduced transconductance and drain resistance.
Innovation Solution
The use of differential pair amplifiers with cross-coupled n-type metal oxide semiconductor cascode transistors and additional capacitance at specific nodes to enhance gain peaking, eliminating the need for inductors and reducing power consumption, while maintaining or improving gain/bandwidth performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If inductive peaking is used to extend bandwidth and resonate out parasitic capacitance, then bandwidth is improved, but device complexity and power consumption increase due to additional inductors and circuit components
Solution Approach 1:
The patent removes inductors from the amplifier circuit entirely, extracting the problematic component that caused complexity while maintaining bandwidth extension through an alternative mechanism (cross-coupled cascode transistors with capacitive loading)
Solution Approach 2:
The patent replaces the inductive peaking mechanism with a capacitive loading mechanism using cross-coupled cascode transistors, substituting one physical principle (inductance) with another (capacitance) to achieve the same bandwidth extension goal without the drawbacks
2Power
If larger input devices or larger resistive loads are introduced to obtain additional gain, then gain is improved, but bandwidth is reduced
Solution Approach 1:
The patent changes the circuit parameters by introducing cross-coupled cascode transistors with specific capacitance values at strategic nodes, altering the frequency response characteristics to achieve gain enhancement without the bandwidth penalty associated with larger passive components
3Power
If additional gain stages are introduced to obtain additional gain, then gain is improved, but power consumption increases
Solution Approach 1:
The patent merges the gain enhancement function into the existing amplifier stage by adding cross-coupled cascode transistors, combining multiple functions (gain, bandwidth extension, parasitic compensation) into a single integrated circuit block rather than adding separate gain stages
4Area of moving object
If CMOS technology scales into nanometer gate length range to increase integration density, then device miniaturization is improved, but transconductance and drain resistance are reduced leading to decreased gain
Solution Approach 1:
The patent creates a scaled-up electrical performance characteristics through the cross-coupled cascode configuration, effectively copying the high-gain behavior of larger devices at the nanometer scale by utilizing the capacitive feedback mechanism to boost transconductance
Data Source
AI summary
Embodiments of the present invention provide differential pair amplifier circuits including cross-coupled cascode transistors. Other embodiments may be described and claimed.