Cross-Coupled Clock Shifter Circuit With Lower Delay and Power
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Solution Overview
Problem
Conventional clock shifter circuits require high-current supply voltages to boost transistor gate voltages above the supply level, leading to increased power consumption and silicon area, and suffer from propagation delays due to series-coupled output switches.
Innovation Solution
A clock shifter circuit design that eliminates the need for boosting transistor gate voltages by using cross-coupled transistor switches and capacitors with long charging time constants, minimizing transistor and capacitor sizes, and removing the series-coupled output switch to reduce power consumption and propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-current supply voltage is used to boost transistor gate voltages above supply level, then transistor switches can be activated, but power consumption increases and silicon area increases
Solution Approach 1:
The patent introduces a bootstrap capacitor as an intermediary energy storage element between the supply voltage and the transistor gate. This capacitor temporarily stores energy to provide the voltage boost needed for gate activation, eliminating the need for high-current supply voltage while still achieving reliable transistor switching. The capacitor acts as a mediator that decouples the gate drive requirement from the main power supply.
Solution Approach 2:
The patent changes the voltage parameter at the transistor gate by using a bootstrap capacitor to create a temporary voltage higher than the supply voltage. This parameter change allows the transistor to be activated with standard supply voltages, reducing power consumption while maintaining reliable switch activation. The voltage parameter is dynamically adjusted through capacitor charging and discharging cycles.
2Stress or pressure
If series-coupled output switch is used to boost output node voltage level, then voltage level can be increased above supply voltage, but propagation delay increases
Solution Approach 1:
The patent removes the series-coupled output switch from the circuit topology. Instead of using a switch in series with the output node to boost voltage, the design extracts the voltage boosting function and implements it through the bootstrap capacitor connected to the gate, which indirectly boosts the output voltage through capacitive coupling. This elimination of the series switch directly reduces propagation delay.
Solution Approach 2:
The patent inverts the conventional approach by not directly boosting the output voltage through a series switch, but instead boosting the gate voltage through a bootstrap capacitor, which then indirectly achieves the desired output voltage level through the transistor's amplification action. This indirect approach reduces the number of switching stages and minimizes propagation delay.
3Area of stationary object
If transistor and capacitor sizes are reduced to minimum, then silicon area decreases, but charging time constant may become too short
Solution Approach 1:
The patent optimizes the capacitor value parameter to achieve a charging time constant that is sufficiently long to allow minimum-sized transistors to charge it completely. By carefully selecting the capacitor size parameter, the design ensures that even with minimum-sized transistors, the charging time constant remains adequate for complete charging within the clock period, while still minimizing overall silicon area.
4Reliability
If long charging time constant is used for capacitors, then transistor switches can be fully charged, but capacitor size increases
Solution Approach 1:
The patent optimizes the capacitor value parameter to achieve the minimum size required for sufficient charging. By carefully selecting the capacitor size, the design ensures that the charging time constant is long enough to allow complete transistor switching while minimizing the capacitor area to reduce overall silicon footprint. This represents an optimized parameter selection that balances charging completeness with area constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design decreases power consumption, reduces silicon area, and improves phase alignment of the output clock signal by allowing minimum-sized transistor switches and capacitors, while minimizing propagation delay and power consumption.
Implementation Method 1
A clock shifter is an electronic circuit that level-shifts an input clock signal from a first voltage domain to a higher (or lower) second voltage domain output clock signal. Clock shifters have been manufactured using a pair of cross-coupled transistor switches with a corresponding pair of coupling capacitors connected between each transistor source and a true or complement version of an input clock signal.
Data Source
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AI summary
A clock shifter circuit may receive a input clock in a first voltage domain and may generate a level-shifted output clock in a second voltage domain. The circuit may include a cross-coupled pair of transistor switches and a pair of capacitors. Each switch may have a drain coupled to one of the capacitors, a source coupled to a circuit supply voltage, and a gate coupled to the other capacitor. One capacitor may receive a true input clock version, while the other may receive a complement version. Each capacitor, in an alternating manner, may activate an opposing transistor switch to charge its capacitor during an active phase of its respective input clock. The circuit may generate the output clock from an output node connected between one of the transistor switches and its capacitor. The output clock may drive a load directly coupled to the output node.